Sylpheed/tools/ppc-manual/vmx/vsubcuw.md

vsubcuw — Vector Subtract Carryout Unsigned Word

Category: VMX (Altivec) · Form: VX · Opcode: 0x10000580

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vsubcuw	vsubcuw	—	Vector Subtract Carryout Unsigned Word

Syntax

vsubcuw [VD], [VA], [VB]

Encoding

vsubcuw — form VX

• Opcode word: 0x10000580
• Primary opcode (bits 0–5): 4
• Extended opcode: 1408
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

Operands

Field	Role	Description
VA	vsubcuw: read	Source A vector register.
VB	vsubcuw: read	Source B vector register.
VD	vsubcuw: write	Destination vector register.

Register Effects

vsubcuw

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vsubcuw

• Canary XML: tools/ppc-instructions.xml — search for mnem="vsubcuw"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1657
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:468
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:651

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vsubcuw(PPCHIRBuilder& f, const InstrData& i) {
  Value* underflow =
      f.VectorCompareUGE(f.LoadVR(i.VX.VA), f.LoadVR(i.VX.VB), INT32_TYPE);
  Value* borrow =
      f.VectorShr(underflow, f.LoadConstantVec128(vec128i(31)), INT32_TYPE);
  f.StoreVR(i.VX.VD, borrow);
  return 0;
}

Special Cases & Edge Conditions

• "Borrow out" producer for unsigned word subtract. Each of the 4 lanes produces 1 if VA.w[i] >= VB.w[i] (no borrow) and 0 otherwise. This is an inverted borrow — conventional borrow would be 1 on underflow, but Altivec's vsubcuw returns the opposite to match the XER[CA] convention used by scalar subfc / subfe.
• Complements vadduwm / vaddcuw for 256-bit (or wider) multi-precision arithmetic. After the lane subtract, chain the 4-bit borrow vector into the next word via vsubeuwm-style helpers (or manual software glue, since Altivec has no direct sube).
• No saturation, no flags, no VSCR effect. Despite being in the "carry" family, vsubcuw doesn't touch VSCR[SAT].
• Big-endian word lanes.
• No VMX128 sibling.

Related Instructions

• vsubuwm — the difference value (unsigned modulo).
• vaddcuw — the paired carry-out producer for unsigned-add.
• vadduwm — unsigned word add (modulo).

IBM Reference

• AIX 7.3 — vsubcuw (Vector Subtract and Write Carry-Out Unsigned Word)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 4 — Integer Arithmetic