f3c512f2ab
The hand-written parts of the manual still described how the retired xenia-rs interpreter behaved: its snapshots, Rust casts and helpers. Each of those 490 statements is now either restated as what Canary's emitters and x64 backend actually do (at the pinned canary_experimental commit), or dropped where it only made sense for xenia-rs. Checking them turned up claims that were wrong, not just outdated: - VSCR[SAT] is never modelled in Canary (DID_SATURATE is a stub and mfvscr cannot see it); the pages said saturating ops set it stickily. - Canary does not implement lswi/lswx/stswi/stswx, dcbi, mtfsb0/mtfsb1, vmsum*, vmhaddshs, vupkhpx/vupklpx, and most SPRs; pages described them as working. - Traps evaluate TO in Canary; stvebx/stvehx/stvewx store one element, not 16 bytes; mtmsrd writes only EE; fres/frsqrte/vrsqrtefp precision claims and the stfs "rounds under RN / sets FPSCR" claim contradicted the spec. - Reservations are a 64 KiB block bitmap plus a value compare, not per-address tracking. Claims that neither Canary's source nor a public spec settles are marked unverified (NI at boot, vmaddcfp128 operand order, estimate bit-exactness). Generated regions are untouched; re-running the generator changes nothing. Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
137 lines
5.6 KiB
Markdown
137 lines
5.6 KiB
Markdown
# `vcfux` — Vector Convert from Unsigned Fixed-Point Word
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> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VX](../forms/VX.md) · **Opcode:** `0x1000030a`
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<!-- GENERATED: BEGIN -->
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## Assembler Mnemonics
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| Mnemonic | XML entry | Flags | Description |
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| --- | --- | --- | --- |
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| `vcfu` | `vcfux` | — | Vector Convert from Unsigned Fixed-Point Word |
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## Syntax
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```asm
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vcfux [VD], [VB], [UIMM]
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```
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## Encoding
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### `vcfux` — form `VX`
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- **Opcode word:** `0x1000030a`
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- **Primary opcode (bits 0–5):** `4`
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- **Extended opcode:** `778`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode (4) |
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| 6–10 | `VRT/VD` | destination vector register |
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| 11–15 | `VRA/VA` | source A vector register |
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| 16–20 | `VRB/VB` | source B vector register |
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| 21–31 | `XO` | extended opcode (11 bits) |
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## Operands
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| Field | Role | Description |
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| --- | --- | --- |
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| `VB` | vcfux: read | Source B vector register. |
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| `UIMM` | vcfux: read | 16-bit unsigned immediate. Zero-extended. |
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| `VD` | vcfux: write | Destination vector register. |
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## Register Effects
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### `vcfux`
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- **Reads (always):** `VB`, `UIMM`
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- **Reads (conditional):** _none_
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- **Writes (always):** `VD`
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- **Writes (conditional):** _none_
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## Status-Register Effects
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_No condition-register or status-register effects._
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## Operation (pseudocode)
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```
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; No hand-written pseudocode for this instruction yet.
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; The authoritative semantics are the Canary emitter snapshot under
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; Implementation References; about half of Canary's emitters open
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; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
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; Every side effect is also enumerated in the Register Effects and
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; Status-Register Effects tables above.
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```
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## C Translation Example
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```c
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/* No hand-written C yet. Translate the Canary emitter snapshot */
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/* under Implementation References; its HIR maps directly: */
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/* f.LoadGPR(n) / f.StoreGPR(n, v) -> r[n] / r[n] = v */
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/* f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n] */
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/* f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters */
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/* wrap them in f.ByteSwap for the big-endian guest value */
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/* f.UpdateCR(n, v) -> CR field n from v's LOW 32 BITS vs 0 */
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/* f.LoadCA / f.StoreCA -> xer.CA; f.StoreSAT -> vscr.SAT */
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/* i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands */
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/* The Register Effects and Status-Register Effects tables above */
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/* enumerate every side effect a faithful translation must emit. */
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```
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## Implementation References
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**`vcfux`**
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- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vcfux"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
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- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:518`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L518)
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- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:320`](../../../crates/sylpheed-ppc/src/opcode.rs#L320)
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- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:617`](../../../crates/sylpheed-ppc/src/decoder.rs#L617)
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<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>
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```cpp
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int InstrEmit_vcfux(PPCHIRBuilder& f, const InstrData& i) {
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return InstrEmit_vcfux_(f, i.VX.VD, i.VX.VB, i.VX.VA);
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}
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// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:507) ──
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int InstrEmit_vcfux_(PPCHIRBuilder& f, uint32_t vd, uint32_t vb,
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uint32_t uimm) {
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// (VD) <- float(VB as unsigned) / 2^uimm
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Value* v = f.VectorConvertI2F(f.LoadVR(vb), ARITHMETIC_UNSIGNED);
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if (uimm) {
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float fuimm = std::ldexp(1.0f, -int(uimm));
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v = f.Mul(v, f.Splat(f.LoadConstantFloat32(fuimm), VEC128_TYPE));
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}
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f.StoreVR(vd, v);
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return 0;
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}
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```
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</details>
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<!-- GENERATED: END -->
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## Special Cases & Edge Conditions
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- **Convert unsigned-Q `uint32` lane to `binary32`.** For each of the four word lanes, `VD[i] = (float)VB[i] / 2^UIMM`. The 5-bit `UIMM` (bits 11..15) gives the Q-format fractional shift, in `0..31`.
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- **Big-endian word lanes.** Lane 0 (`VD[0..3]` after `stvx`) is the most-significant word.
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- **Use case.** Unsigned Q-format fixed-point → IEEE float; common for normalised colour channels (`vcfux vD, vColor, 8` rescales `0..255` to `0..0.996`).
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- **Inexact rounding.** Magnitudes above `2^24` lose precision. Default rounding is round-to-nearest-even; VMX has no per-instruction rounding control.
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- **`VSCR[NJ]`** affects sub-normal outputs. Canary multiplies by `2^-UIMM` under its VMX MXCSR, which flushes such results to zero while `NJ` is set.
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- **No `VSCR[SAT]`, no XER changes, no exceptions.**
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- **No VMX128 sibling.**
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- **Round-trip caveat.** Pair with [`vctuxs`](vctuxs.md) for the inverse — but the inverse saturates rather than wraps, so floats above `2^32 − 1` clamp to `0xFFFFFFFF` and stick `VSCR[SAT]`.
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## Related Instructions
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- [`vcfsx`](vcfsx.md) — same shape, signed source.
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- [`vctuxs`](vctuxs.md) — inverse: float → unsigned-Q `uint32` with saturation.
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- [`vctsxs`](vctsxs.md) — inverse: float → signed-Q `int32` with saturation.
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- [`vrfin`](vrfin.md), [`vrfiz`](vrfiz.md) — float-to-integer rounding modes for the un-scaled case.
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## IBM Reference
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- [AIX 7.3 — `vcfux` (Vector Convert from Unsigned Fixed-Point Word)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-vcfux-vector-convert-from-unsigned-fixed-point-word-instruction)
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- [IBM AltiVec Technology Programmer's Interface Manual, Chapter 5 — Conversion Instructions](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf)
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