f3c512f2ab
The hand-written parts of the manual still described how the retired xenia-rs interpreter behaved: its snapshots, Rust casts and helpers. Each of those 490 statements is now either restated as what Canary's emitters and x64 backend actually do (at the pinned canary_experimental commit), or dropped where it only made sense for xenia-rs. Checking them turned up claims that were wrong, not just outdated: - VSCR[SAT] is never modelled in Canary (DID_SATURATE is a stub and mfvscr cannot see it); the pages said saturating ops set it stickily. - Canary does not implement lswi/lswx/stswi/stswx, dcbi, mtfsb0/mtfsb1, vmsum*, vmhaddshs, vupkhpx/vupklpx, and most SPRs; pages described them as working. - Traps evaluate TO in Canary; stvebx/stvehx/stvewx store one element, not 16 bytes; mtmsrd writes only EE; fres/frsqrte/vrsqrtefp precision claims and the stfs "rounds under RN / sets FPSCR" claim contradicted the spec. - Reservations are a 64 KiB block bitmap plus a value compare, not per-address tracking. Claims that neither Canary's source nor a public spec settles are marked unverified (NI at boot, vmaddcfp128 operand order, estimate bit-exactness). Generated regions are untouched; re-running the generator changes nothing. Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
185 lines
7.4 KiB
Markdown
185 lines
7.4 KiB
Markdown
# `vmaxfp` — Vector Maximum Floating Point
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> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VX](../forms/VX.md) · **Opcode:** `0x1000040a`
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<!-- GENERATED: BEGIN -->
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## Assembler Mnemonics
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| Mnemonic | XML entry | Flags | Description |
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| --- | --- | --- | --- |
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| `vmaxfp` | `vmaxfp` | — | Vector Maximum Floating Point |
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| `vmaxfp128` | `vmaxfp128` | — | Vector128 Maximum Floating Point |
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## Syntax
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```asm
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vmaxfp [VD], [VA], [VB]
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vmaxfp128 [VD], [VA], [VB]
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```
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## Encoding
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### `vmaxfp` — form `VX`
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- **Opcode word:** `0x1000040a`
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- **Primary opcode (bits 0–5):** `4`
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- **Extended opcode:** `1034`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode (4) |
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| 6–10 | `VRT/VD` | destination vector register |
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| 11–15 | `VRA/VA` | source A vector register |
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| 16–20 | `VRB/VB` | source B vector register |
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| 21–31 | `XO` | extended opcode (11 bits) |
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### `vmaxfp128` — form `VX128`
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- **Opcode word:** `0x18000280`
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- **Primary opcode (bits 0–5):** `6`
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- **Extended opcode:** `640`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode (4 or 5) |
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| 6–10 | `VD128l` | destination low 5 bits |
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| 11–15 | `VA128l` | source A low 5 bits |
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| 16–20 | `VB128l` | source B low 5 bits |
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| 21 | `VA128H` | source A high bit |
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| 22 | `—` | reserved |
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| 23–25 | `VC` | optional VC / XO sub-field |
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| 26 | `VA128h` | source A middle bit |
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| 27 | `—` | reserved |
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| 28–29 | `VD128h` | destination high 2 bits |
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| 30–31 | `VB128h` | source B high 2 bits |
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## Operands
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| Field | Role | Description |
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| --- | --- | --- |
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| `VA` | vmaxfp: read; vmaxfp128: read | Source A vector register. |
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| `VB` | vmaxfp: read; vmaxfp128: read | Source B vector register. |
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| `VD` | vmaxfp: write; vmaxfp128: write | Destination vector register. |
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## Register Effects
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### `vmaxfp`
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- **Reads (always):** `VA`, `VB`
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- **Reads (conditional):** _none_
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- **Writes (always):** `VD`
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- **Writes (conditional):** _none_
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### `vmaxfp128`
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- **Reads (always):** `VA`, `VB`
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- **Reads (conditional):** _none_
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- **Writes (always):** `VD`
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- **Writes (conditional):** _none_
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## Status-Register Effects
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_No condition-register or status-register effects._
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## Operation (pseudocode)
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```
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; No hand-written pseudocode for this instruction yet.
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; The authoritative semantics are the Canary emitter snapshot under
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; Implementation References; about half of Canary's emitters open
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; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
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; Every side effect is also enumerated in the Register Effects and
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; Status-Register Effects tables above.
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```
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## C Translation Example
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```c
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/* No hand-written C yet. Translate the Canary emitter snapshot */
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/* under Implementation References; its HIR maps directly: */
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/* f.LoadGPR(n) / f.StoreGPR(n, v) -> r[n] / r[n] = v */
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/* f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n] */
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/* f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters */
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/* wrap them in f.ByteSwap for the big-endian guest value */
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/* f.UpdateCR(n, v) -> CR field n from v's LOW 32 BITS vs 0 */
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/* f.LoadCA / f.StoreCA -> xer.CA; f.StoreSAT -> vscr.SAT */
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/* i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands */
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/* The Register Effects and Status-Register Effects tables above */
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/* enumerate every side effect a faithful translation must emit. */
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```
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## Implementation References
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**`vmaxfp`**
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- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vmaxfp"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
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- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:818`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L818)
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- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:350`](../../../crates/sylpheed-ppc/src/opcode.rs#L350)
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- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:637`](../../../crates/sylpheed-ppc/src/decoder.rs#L637)
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<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>
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```cpp
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int InstrEmit_vmaxfp(PPCHIRBuilder& f, const InstrData& i) {
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return InstrEmit_vmaxfp_(f, i.VX.VD, i.VX.VA, i.VX.VB);
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}
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// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:812) ──
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int InstrEmit_vmaxfp_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb) {
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// (VD) <- max((VA), (VB))
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Value* v = f.Max(f.LoadVR(va), f.LoadVR(vb));
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f.StoreVR(vd, v);
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return 0;
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}
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```
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</details>
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**`vmaxfp128`**
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- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vmaxfp128"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
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- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:821`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L821)
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- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:351`](../../../crates/sylpheed-ppc/src/opcode.rs#L351)
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- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:811`](../../../crates/sylpheed-ppc/src/decoder.rs#L811)
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<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>
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```cpp
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int InstrEmit_vmaxfp128(PPCHIRBuilder& f, const InstrData& i) {
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return InstrEmit_vmaxfp_(f, VX128_VD128, VX128_VA128, VX128_VB128);
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}
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// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:812) ──
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int InstrEmit_vmaxfp_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb) {
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// (VD) <- max((VA), (VB))
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Value* v = f.Max(f.LoadVR(va), f.LoadVR(vb));
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f.StoreVR(vd, v);
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return 0;
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}
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```
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</details>
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<!-- GENERATED: END -->
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## Special Cases & Edge Conditions
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- **Per-lane IEEE max.** Four word lanes; `VD[i] = (VA[i] > VB[i]) ? VA[i] : VB[i]`.
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- **NaN propagation.** The IBM manual specifies "the larger of `VA[i]` and `VB[i]`, with NaN handling such that any NaN input yields a NaN result". Canary's x64 `MAX` matches: it blends the NaN back in when either lane is NaN (`VA`'s when both are), and takes `max(+0, −0) = +0` by AND-ing both operand orders of `vmaxps`.
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- **Sign of zero.** Canary's `vmaxfp(+0, -0)` returns `+0`: it ANDs both operand orders of `vmaxps` (its comment: "if 0 and -0, return 0! opposite of minfp"). What Xenon returns is unverified.
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- **`VSCR[NJ]` denormals.** With `NJ = 1` (Xenon default), denormal inputs are flushed to `±0` before comparison.
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- **No `VSCR[SAT]` change, no XER change, no exceptions.**
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- **Big-endian word lanes.** Lane 0 is the most-significant word.
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- **Aliasing legal.** `vmaxfp v3, v3, v4` is the standard "clamp from below by `v4`" idiom.
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- **VMX128 sibling (`vmaxfp128`).** Identical comparator semantics with the extended encoding.
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## Related Instructions
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- [`vminfp`](vminfp.md) — the per-lane minimum.
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- [`vcmpgtfp`](vcmpgtfp.md), [`vcmpgefp`](vcmpgefp.md) — separate compare-and-mask path.
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- [`vsel`](vsel.md) — combine masks with arbitrary alternatives.
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- [`vmaddfp`](vmaddfp.md) — fused multiply-add when the max is part of a polynomial.
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- [`vmaxsw`](vmaxsw.md) — integer-word max if the lanes are signed integers.
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## IBM Reference
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- [AIX 7.3 — `vmaxfp` (Vector Maximum Floating Point)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-vmaxfp-vector-maximum-floating-point-instruction)
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- [IBM AltiVec Technology Programmer's Interface Manual, Chapter 5 — Floating-Point Min/Max](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf)
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