Sylpheed/tools/ppc-manual/vmx/vmhaddshs.md

vmhaddshs — Vector Multiply-High and Add Signed Signed Half Word Saturate

Category: VMX (Altivec) · Form: VA · Opcode: 0x10000020

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vmhaddshs	vmhaddshs	—	Vector Multiply-High and Add Signed Signed Half Word Saturate

Syntax

vmhaddshs [VD], [VA], [VB], [VC]

Encoding

vmhaddshs — form VA

• Opcode word: 0x10000020
• Primary opcode (bits 0–5): 4
• Extended opcode: 32
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT	destination vector register
11–15	VRA	source A
16–20	VRB	source B
21–25	VRC	source C / shift
26–31	XO	extended opcode (6 bits)

Operands

Field	Role	Description
VA	vmhaddshs: read	Source A vector register.
VB	vmhaddshs: read	Source B vector register.
VC	vmhaddshs: read	Source C vector register / 3-bit selector.
VD	vmhaddshs: write	Destination vector register.
VSCR	vmhaddshs: write	Vector Status and Control Register (NJ/SAT bits).

Register Effects

vmhaddshs

• Reads (always): VA, VB, VC
• Reads (conditional): none
• Writes (always): VD, VSCR
• Writes (conditional): none

Status-Register Effects

• vmhaddshs: VSCR[SAT] may be stickied on saturating vector operations.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vmhaddshs

• Canary XML: tools/ppc-instructions.xml — search for mnem="vmhaddshs"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:870
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:358
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:691

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vmhaddshs(PPCHIRBuilder& f, const InstrData& i) {
  XEINSTRNOTIMPLEMENTED();
  return 1;
}

Special Cases & Edge Conditions

• Q15 fixed-point multiply-add, saturating. Eight half-word lanes; per lane:

  prod  = (int16(VA[i]) * int16(VB[i])) >> 15      ; truncating, no rounding
  VD[i] = clamp(prod + int16(VC[i]), -32768, +32767)
  

  The "h" in the mnemonic is "high half" — only the upper 17 bits of the 32-bit signed product survive (after >>15), then the accumulator is added.
• Truncating, not rounding. Bit 14 of the product is discarded silently. Use vmhraddshs when half-up rounding is needed (it adds 0x4000 to the product before the shift). The two are otherwise identical.
• VSCR[SAT] is sticky-set if prod + VC[i] overflows int16. Cleared only by mtvscr. ⚠️ Canary does not implement vmhaddshs: its emitter is XEINSTRNOTIMPLEMENTED, so translating one logs "Unimplemented instr" and, with the default break_on_unimplemented_instructions, breaks.
• Pathological case 0x8000 * 0x8000 >> 15. Equals 0x10000 in the un-saturated product = +32768 after the shift, which overflows int16 even before adding VC. The clamp then produces +32767 and stickies SAT. This is the classic Q15 "minus-one-times-minus-one" gotcha.
• Big-endian half lanes. Lane 0 is the most-significant half.
• No XER changes, no exceptions.
• No VMX128 sibling.
• Common usage. Q15 IIR / FIR filter taps, fixed-point matrix-vector multiplies for audio.

Related Instructions

• vmhraddshs — same operation with rounded multiply (+0x4000 before >> 15).
• vmladduhm — same shape, modulo (no shift, no saturate), unsigned half lanes.
• vmsumshs, vmsumshm — multiply-sum across pairs of lanes.
• vaddshs, vmaxsh — saturating add and max at the same lane width, useful in the same DSP kernels.

IBM Reference

• AIX 7.3 — vmhaddshs (Vector Multiply-High and Add Signed Half Word Saturate)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Multiply-Add Family