Sylpheed/tools/ppc-manual/vmx/vmrghb.md

vmrghb — Vector Merge High Byte

Category: VMX (Altivec) · Form: VX · Opcode: 0x1000000c

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vmrghb	vmrghb	—	Vector Merge High Byte

Syntax

vmrghb [VD], [VA], [VB]

Encoding

vmrghb — form VX

• Opcode word: 0x1000000c
• Primary opcode (bits 0–5): 4
• Extended opcode: 12
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

Operands

Field	Role	Description
VA	vmrghb: read	Source A vector register.
VB	vmrghb: read	Source B vector register.
VD	vmrghb: write	Destination vector register.

Register Effects

vmrghb

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vmrghb

• Canary XML: tools/ppc-instructions.xml — search for mnem="vmrghb"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:943
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:369
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:554

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vmrghb(PPCHIRBuilder& f, const InstrData& i) {
  // (VD.b[i]) = (VA.b[i])
  // (VD.b[i+1]) = (VB.b[i+1])
  // ...
  Value* v =
      f.Permute(f.LoadConstantVec128(vec128b(0, 16, 1, 17, 2, 18, 3, 19, 4, 20,
                                             5, 21, 6, 22, 7, 23)),
                f.LoadVR(i.VX.VA), f.LoadVR(i.VX.VB), INT8_TYPE);
  f.StoreVR(i.VX.VD, v);
  return 0;
}

Special Cases & Edge Conditions

• Interleave the high (most-significant) eight bytes of two vectors. After execution, VD = {VA[0], VB[0], VA[1], VB[1], …, VA[7], VB[7]}, i.e. the eight high-order bytes of VA are interleaved with the eight high-order bytes of VB. Because lane 0 is the most-significant byte (big-endian indexing), "high" means the byte that appears at the lowest address after stvx.
• Pairs with vmrglb. Together they cover all 32 input bytes — vmrghb produces output of bytes 0..7 from each source, vmrglb of bytes 8..15. Two vmrg* instructions plus a stvx of each output produces the AoS-from-SoA transpose.
• Useful for unpacking 8-bit channels. vmrghb vRG, vR, vG followed by vmrghb vRGBA, vRG, vBA interleaves four byte-streams into RGBA pixels.
• No VSCR interaction, no XER, no exceptions. Pure permute.
• Aliasing legal. vmrghb v3, v3, v3 doubles each high byte of v3.
• No VMX128 sibling.
• Equivalent to x86 _mm_unpackhi_epi8 with operand orientation swapped (Altivec uses big-endian lane numbering, x86 little-endian, so "high" on PPC ↔ "low" lane indices on x86).

Related Instructions

• vmrglb — the "low half" mirror.
• vmrghh, vmrghw — high-half merge at half / word width.
• vperm — fully programmable permute when neither merge half fits.
• vsldoi — static-offset shift-double, often paired with vmrg* for AoS↔SoA conversions.
• vupkhsb — sign-extending unpack of the high half.

IBM Reference

• AIX 7.3 — vmrghb (Vector Merge High Byte)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Permute / Merge