9bfe96e44d
- Category pages linked each family as `<slug>.md`, relative to categories/, where no family page lives. They now link `../<category>/<slug>.md`. - Form pages linked a member into its *own* category directory, so every VMX128 sibling (`vsldoi128`) pointed at vmx128/ although its family page is under vmx/. They now link into the family's directory. - Hand-written "Related" and sibling mentions linked other categories' pages as if they were in the same directory. 109 are retargeted through the page index; 29 that pointed a family page at itself (`vrefp128` on vrefp.md) and 6 naming instructions the manual has no page for are plain text now. Regenerated at the existing Canary pin (f21ebd49e): upstream has moved on, and re-pinning belongs in its own change. The generator reports 0 family pages changed and is idempotent; the only dead links left are TEMPLATE.md's placeholders. Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
132 lines
5.5 KiB
Markdown
132 lines
5.5 KiB
Markdown
# `vmrghb` — Vector Merge High Byte
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> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VX](../forms/VX.md) · **Opcode:** `0x1000000c`
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<!-- GENERATED: BEGIN -->
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## Assembler Mnemonics
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| Mnemonic | XML entry | Flags | Description |
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| --- | --- | --- | --- |
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| `vmrghb` | `vmrghb` | — | Vector Merge High Byte |
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## Syntax
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```asm
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vmrghb [VD], [VA], [VB]
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```
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## Encoding
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### `vmrghb` — form `VX`
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- **Opcode word:** `0x1000000c`
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- **Primary opcode (bits 0–5):** `4`
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- **Extended opcode:** `12`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode (4) |
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| 6–10 | `VRT/VD` | destination vector register |
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| 11–15 | `VRA/VA` | source A vector register |
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| 16–20 | `VRB/VB` | source B vector register |
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| 21–31 | `XO` | extended opcode (11 bits) |
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## Operands
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| Field | Role | Description |
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| --- | --- | --- |
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| `VA` | vmrghb: read | Source A vector register. |
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| `VB` | vmrghb: read | Source B vector register. |
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| `VD` | vmrghb: write | Destination vector register. |
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## Register Effects
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### `vmrghb`
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- **Reads (always):** `VA`, `VB`
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- **Reads (conditional):** _none_
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- **Writes (always):** `VD`
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- **Writes (conditional):** _none_
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## Status-Register Effects
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_No condition-register or status-register effects._
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## Operation (pseudocode)
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```
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; No hand-written pseudocode for this instruction yet.
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; The authoritative semantics are the Canary emitter snapshot under
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; Implementation References; about half of Canary's emitters open
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; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
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; Every side effect is also enumerated in the Register Effects and
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; Status-Register Effects tables above.
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```
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## C Translation Example
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```c
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/* No hand-written C yet. Translate the Canary emitter snapshot */
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/* under Implementation References; its HIR maps directly: */
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/* f.LoadGPR(n) / f.StoreGPR(n, v) -> r[n] / r[n] = v */
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/* f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n] */
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/* f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters */
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/* wrap them in f.ByteSwap for the big-endian guest value */
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/* f.UpdateCR(n, v) -> CR field n from v's LOW 32 BITS vs 0 */
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/* f.LoadCA / f.StoreCA -> xer.CA; f.StoreSAT -> vscr.SAT */
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/* i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands */
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/* The Register Effects and Status-Register Effects tables above */
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/* enumerate every side effect a faithful translation must emit. */
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```
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## Implementation References
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**`vmrghb`**
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- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vmrghb"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
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- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:943`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L943)
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- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:369`](../../../crates/sylpheed-ppc/src/opcode.rs#L369)
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- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:554`](../../../crates/sylpheed-ppc/src/decoder.rs#L554)
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<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>
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```cpp
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int InstrEmit_vmrghb(PPCHIRBuilder& f, const InstrData& i) {
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// (VD.b[i]) = (VA.b[i])
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// (VD.b[i+1]) = (VB.b[i+1])
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// ...
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Value* v =
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f.Permute(f.LoadConstantVec128(vec128b(0, 16, 1, 17, 2, 18, 3, 19, 4, 20,
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5, 21, 6, 22, 7, 23)),
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f.LoadVR(i.VX.VA), f.LoadVR(i.VX.VB), INT8_TYPE);
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f.StoreVR(i.VX.VD, v);
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return 0;
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}
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```
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</details>
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<!-- GENERATED: END -->
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## Special Cases & Edge Conditions
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- **Interleave the high (most-significant) eight bytes** of two vectors. After execution, `VD = {VA[0], VB[0], VA[1], VB[1], …, VA[7], VB[7]}`, i.e. the eight high-order bytes of `VA` are interleaved with the eight high-order bytes of `VB`. Because lane 0 is the most-significant byte (big-endian indexing), "high" means the byte that appears at the lowest address after `stvx`.
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- **Pairs with [`vmrglb`](vmrglb.md).** Together they cover all 32 input bytes — `vmrghb` produces output of bytes 0..7 from each source, `vmrglb` of bytes 8..15. Two `vmrg*` instructions plus a [`stvx`](../memory/stvx.md) of each output produces the AoS-from-SoA transpose.
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- **Useful for unpacking 8-bit channels.** `vmrghb vRG, vR, vG` followed by `vmrghb vRGBA, vRG, vBA` interleaves four byte-streams into RGBA pixels.
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- **No `VSCR` interaction, no XER, no exceptions.** Pure permute.
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- **Aliasing legal.** `vmrghb v3, v3, v3` doubles each high byte of `v3`.
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- **No VMX128 sibling.**
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- **Equivalent to x86 `_mm_unpackhi_epi8`** with operand orientation swapped (Altivec uses big-endian lane numbering, x86 little-endian, so "high" on PPC ↔ "low" lane indices on x86).
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## Related Instructions
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- [`vmrglb`](vmrglb.md) — the "low half" mirror.
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- [`vmrghh`](vmrghh.md), [`vmrghw`](vmrghw.md) — high-half merge at half / word width.
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- [`vperm`](vperm.md) — fully programmable permute when neither merge half fits.
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- [`vsldoi`](vsldoi.md) — static-offset shift-double, often paired with `vmrg*` for AoS↔SoA conversions.
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- [`vupkhsb`](vupkhsb.md) — sign-extending unpack of the high half.
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## IBM Reference
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- [AIX 7.3 — `vmrghb` (Vector Merge High Byte)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-vmrghb-vector-merge-high-byte-instruction)
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- [IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Permute / Merge](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf)
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