f3c512f2ab
The hand-written parts of the manual still described how the retired xenia-rs interpreter behaved: its snapshots, Rust casts and helpers. Each of those 490 statements is now either restated as what Canary's emitters and x64 backend actually do (at the pinned canary_experimental commit), or dropped where it only made sense for xenia-rs. Checking them turned up claims that were wrong, not just outdated: - VSCR[SAT] is never modelled in Canary (DID_SATURATE is a stub and mfvscr cannot see it); the pages said saturating ops set it stickily. - Canary does not implement lswi/lswx/stswi/stswx, dcbi, mtfsb0/mtfsb1, vmsum*, vmhaddshs, vupkhpx/vupklpx, and most SPRs; pages described them as working. - Traps evaluate TO in Canary; stvebx/stvehx/stvewx store one element, not 16 bytes; mtmsrd writes only EE; fres/frsqrte/vrsqrtefp precision claims and the stfs "rounds under RN / sets FPSCR" claim contradicted the spec. - Reservations are a 64 KiB block bitmap plus a value compare, not per-address tracking. Claims that neither Canary's source nor a public spec settles are marked unverified (NI at boot, vmaddcfp128 operand order, estimate bit-exactness). Generated regions are untouched; re-running the generator changes nothing. Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
183 lines
7.2 KiB
Markdown
183 lines
7.2 KiB
Markdown
# `vnor` — Vector Logical NOR
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> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VX](../forms/VX.md) · **Opcode:** `0x10000504`
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<!-- GENERATED: BEGIN -->
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## Assembler Mnemonics
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| Mnemonic | XML entry | Flags | Description |
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| --- | --- | --- | --- |
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| `vnor` | `vnor` | — | Vector Logical NOR |
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| `vnor128` | `vnor128` | — | Vector128 Logical NOR |
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## Syntax
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```asm
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vnor [VD], [VA], [VB]
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vnor128 [VD], [VA], [VB]
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```
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## Encoding
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### `vnor` — form `VX`
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- **Opcode word:** `0x10000504`
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- **Primary opcode (bits 0–5):** `4`
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- **Extended opcode:** `1284`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode (4) |
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| 6–10 | `VRT/VD` | destination vector register |
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| 11–15 | `VRA/VA` | source A vector register |
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| 16–20 | `VRB/VB` | source B vector register |
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| 21–31 | `XO` | extended opcode (11 bits) |
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### `vnor128` — form `VX128`
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- **Opcode word:** `0x14000290`
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- **Primary opcode (bits 0–5):** `5`
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- **Extended opcode:** `656`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode (4 or 5) |
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| 6–10 | `VD128l` | destination low 5 bits |
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| 11–15 | `VA128l` | source A low 5 bits |
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| 16–20 | `VB128l` | source B low 5 bits |
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| 21 | `VA128H` | source A high bit |
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| 22 | `—` | reserved |
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| 23–25 | `VC` | optional VC / XO sub-field |
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| 26 | `VA128h` | source A middle bit |
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| 27 | `—` | reserved |
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| 28–29 | `VD128h` | destination high 2 bits |
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| 30–31 | `VB128h` | source B high 2 bits |
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## Operands
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| Field | Role | Description |
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| --- | --- | --- |
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| `VA` | vnor: read; vnor128: read | Source A vector register. |
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| `VB` | vnor: read; vnor128: read | Source B vector register. |
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| `VD` | vnor: write; vnor128: write | Destination vector register. |
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## Register Effects
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### `vnor`
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- **Reads (always):** `VA`, `VB`
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- **Reads (conditional):** _none_
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- **Writes (always):** `VD`
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- **Writes (conditional):** _none_
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### `vnor128`
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- **Reads (always):** `VA`, `VB`
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- **Reads (conditional):** _none_
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- **Writes (always):** `VD`
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- **Writes (conditional):** _none_
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## Status-Register Effects
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_No condition-register or status-register effects._
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## Operation (pseudocode)
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```
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; No hand-written pseudocode for this instruction yet.
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; The authoritative semantics are the Canary emitter snapshot under
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; Implementation References; about half of Canary's emitters open
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; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
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; Every side effect is also enumerated in the Register Effects and
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; Status-Register Effects tables above.
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```
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## C Translation Example
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```c
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/* No hand-written C yet. Translate the Canary emitter snapshot */
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/* under Implementation References; its HIR maps directly: */
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/* f.LoadGPR(n) / f.StoreGPR(n, v) -> r[n] / r[n] = v */
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/* f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n] */
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/* f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters */
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/* wrap them in f.ByteSwap for the big-endian guest value */
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/* f.UpdateCR(n, v) -> CR field n from v's LOW 32 BITS vs 0 */
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/* f.LoadCA / f.StoreCA -> xer.CA; f.StoreSAT -> vscr.SAT */
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/* i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands */
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/* The Register Effects and Status-Register Effects tables above */
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/* enumerate every side effect a faithful translation must emit. */
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```
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## Implementation References
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**`vnor`**
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- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vnor"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
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- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:1144`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L1144)
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- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:396`](../../../crates/sylpheed-ppc/src/opcode.rs#L396)
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- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:649`](../../../crates/sylpheed-ppc/src/decoder.rs#L649)
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<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>
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```cpp
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int InstrEmit_vnor(PPCHIRBuilder& f, const InstrData& i) {
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return InstrEmit_vnor_(f, i.VX.VD, i.VX.VA, i.VX.VB);
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}
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// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:1138) ──
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int InstrEmit_vnor_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb) {
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// VD <- ¬((VA) | (VB))
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Value* v = f.Not(f.Or(f.LoadVR(va), f.LoadVR(vb)));
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f.StoreVR(vd, v);
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return 0;
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}
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```
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</details>
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**`vnor128`**
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- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vnor128"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
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- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:1147`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L1147)
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- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:397`](../../../crates/sylpheed-ppc/src/opcode.rs#L397)
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- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:738`](../../../crates/sylpheed-ppc/src/decoder.rs#L738)
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<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>
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```cpp
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int InstrEmit_vnor128(PPCHIRBuilder& f, const InstrData& i) {
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return InstrEmit_vnor_(f, VX128_VD128, VX128_VA128, VX128_VB128);
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}
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// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:1138) ──
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int InstrEmit_vnor_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb) {
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// VD <- ¬((VA) | (VB))
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Value* v = f.Not(f.Or(f.LoadVR(va), f.LoadVR(vb)));
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f.StoreVR(vd, v);
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return 0;
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}
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```
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</details>
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<!-- GENERATED: END -->
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## Special Cases & Edge Conditions
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- **Bitwise NOR across the full 128-bit register.** `VD = ~(VA | VB)`. The operation is lane-agnostic; PPC documents it per-bit, and Canary emits `Not(Or(VA, VB))` over the whole vector — identical to any 32-bit, 16-bit or 8-bit decomposition.
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- **`vnor VD, VA, VA` is the idiomatic `vnot`** (bitwise complement of `VA`). No dedicated `vnot` exists in base Altivec.
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- **Aliasing is legal.** `vnor v3, v3, v4` or `vnor v3, v3, v3` are well-defined and common.
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- **No flags.** No CR, XER, VSCR side-effect.
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- **VMX128 sibling `vnor128`** provides the same op with access to `v0..v127`; Canary's `vnor128` decodes the 7-bit indices and shares `vnor`'s body.
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- **Useful for mask inversion.** When a compare result needs to be inverted — e.g. "where not equal" — `vnor` of the compare result with itself is cheaper than a dedicated inversion.
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## Related Instructions
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- [`vand`](vand.md) — bitwise AND.
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- [`vandc`](vandc.md) — `VA & ~VB` (useful as a fused inversion on the B side).
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- [`vor`](vor.md), [`vxor`](vxor.md) — complete the boolean-primitive set.
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- [`vsel`](vsel.md) — three-input bit-select; often fed by the inverse of a compare mask.
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- [`vcmpequb`](vcmpequb.md) and related compares — produce the masks `vnor` is typically applied to.
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## IBM Reference
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- [AIX 7.3 — `vnor` (Vector Logical NOR)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-vnor-vector-logical-nor-instruction)
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- [IBM AltiVec Technology Programmer's Interface Manual, Chapter 3 — Logical Operations](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf)
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