Sylpheed/tools/ppc-manual/alu/addmex.md

addmex — Add to Minus One Extended

Category: Integer ALU · Form: XO · Opcode: 0x7c0001d4

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
addme	addmex	—	Add to Minus One Extended
addmeo	addmex	OE=1	Add to Minus One Extended
addme.	addmex	Rc=1	Add to Minus One Extended
addmeo.	addmex	OE=1, Rc=1	Add to Minus One Extended

Syntax

addme[OE][Rc] [RD], [RA]

Encoding

addmex — form XO

• Opcode word: 0x7c0001d4
• Primary opcode (bits 0–5): 31
• Extended opcode: 234
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (31)
6–10	RT	destination GPR
11–15	RA	source A
16–20	RB	source B
21	OE	overflow-enable flag
22–30	XO	extended opcode (9 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RA	addmex: read	Source GPR (r0–r31).
CA	addmex: read; addmex: write	XER[CA] carry bit. Read by add-with-carry/subtract-with-borrow instructions, written by carrying instructions.
RD	addmex: write	Destination GPR.
OE	addmex: write (conditional)	Overflow-enable bit. When 1, the instruction updates XER[OV] and stickies XER[SO] on signed overflow.
CR	addmex: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

addmex

• Reads (always): RA, CA
• Reads (conditional): none
• Writes (always): RD, CA
• Writes (conditional): OE, CR

Status-Register Effects

• addmex: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.; XER[OV] ← signed-overflow(result); XER[SO] stickies, when OE=1.; XER[CA] ← carry-out of the add / borrow-in of the subtract (always).

Operation (pseudocode)

RT <- (RA) + CA + 0xFFFF_FFFF_FFFF_FFFF
CA <- carry_out

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

addmex

• Canary XML: tools/ppc-instructions.xml — search for mnem="addmex"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_alu.cc:152
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:14
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:988

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_addmex(PPCHIRBuilder& f, const InstrData& i) {
  // RT <- (RA) + CA - 1
  // CA <- carry bit
  Value* ra = f.LoadGPR(i.XO.RA);
  Value* v = f.AddWithCarry(ra, f.LoadConstantInt64(-1), f.LoadCA());
  f.StoreGPR(i.XO.RT, v);
  if (i.XO.OE) {
    // With XER[SO] update too.
    // e.update_xer_with_overflow_and_carry(b.CreateExtractValue(v, 1));
    XEINSTRNOTIMPLEMENTED();
  } else {
    // Just CA update.
    f.StoreCA(AddWithCarryDidCarry(f, ra, f.LoadConstantInt64(-1), f.LoadCA()));
  }
  if (i.XO.Rc) {
    f.UpdateCR(0, v);
  }
  return 0;
}

Special Cases & Edge Conditions

• No RB field used. addmex is encoded in XO-form but ignores the RB slot — assemblers must still emit a value (typically zero). Disassemblers that parse a non-zero RB should not flag it as illegal; it is simply unused.
• Operation is RA + CA + (−1), i.e. RA - 1 + CA. Used to terminate a multi-word subtract chain when the high source word is implicitly all-ones (e.g. computing -x as ~x + 1 across 128 bits).
• Carry-out predicate is RA != 0 OR CA != 0. Equivalently, CA' = NOT(RA == 0 AND CA == 0): adding −1 to anything except a zero-with-no-carry produces a carry-out. Canary evaluates it on the low word (AddWithCarryDidCarry truncates to INT32), so there the predicate is RA[32:63] != 0 OR CA != 0.
• Overflow not implemented in Canary. The OE=1 branch is XEINSTRNOTIMPLEMENTED() and does not store CA either; spec says set XER[OV] if the signed result wraps.
• 64-bit CR update on Xenon, 32-bit in Canary — f.UpdateCR(0, v), the same INT32 truncation as the rest of the add family.
• XER[CA] must be initialised by an earlier carrying instruction. addme is a terminator, not a seed.

Related Instructions

• addzex — terminate a chain with RA + 0 + CA (no −1).
• addex — middle-of-chain RA + RB + CA.
• addcx — seeds a chain.
• subfmex — subtract dual: ~RA + (−1) + CA.
• negx — single-instruction two's-complement negate.

IBM Reference

• AIX 7.3 — addme (Add to Minus One Extended)