Sylpheed/tools/ppc-manual/alu/addex.md

addex — Add Extended

Category: Integer ALU · Form: XO · Opcode: 0x7c000114

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
adde	addex	—	Add Extended
addeo	addex	OE=1	Add Extended
adde.	addex	Rc=1	Add Extended
addeo.	addex	OE=1, Rc=1	Add Extended

Syntax

adde[OE][Rc] [RD], [RA], [RB]

Encoding

addex — form XO

• Opcode word: 0x7c000114
• Primary opcode (bits 0–5): 31
• Extended opcode: 138
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (31)
6–10	RT	destination GPR
11–15	RA	source A
16–20	RB	source B
21	OE	overflow-enable flag
22–30	XO	extended opcode (9 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RA	addex: read	Source GPR (r0–r31).
RB	addex: read	Source GPR.
CA	addex: read	XER[CA] carry bit. Read by add-with-carry/subtract-with-borrow instructions, written by carrying instructions.
RD	addex: write	Destination GPR.
OE	addex: write (conditional)	Overflow-enable bit. When 1, the instruction updates XER[OV] and stickies XER[SO] on signed overflow.
CR	addex: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

addex

• Reads (always): RA, RB, CA
• Reads (conditional): none
• Writes (always): RD
• Writes (conditional): OE, CR

Status-Register Effects

• addex: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.; XER[OV] ← signed-overflow(result); XER[SO] stickies, when OE=1.

Operation (pseudocode)

RT <- (RA) + (RB) + CA
CA <- carry_out_of_the_add

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

addex

• Canary XML: tools/ppc-instructions.xml — search for mnem="addex"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_alu.cc:83
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:9
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:983

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_addex(PPCHIRBuilder& f, const InstrData& i) {
  // RD <- (RA) + (RB) + XER[CA]
  // CA <- carry bit
  Value* ra = f.LoadGPR(i.XO.RA);
  Value* rb = f.LoadGPR(i.XO.RB);
  Value* v = f.AddWithCarry(ra, rb, f.LoadCA());
  f.StoreGPR(i.XO.RT, v);
  f.StoreCA(AddWithCarryDidCarry(f, ra, rb, f.LoadCA()));
  if (i.XO.Rc) {
    f.UpdateCR(0, v);
  }
  if (i.XO.OE) {
    // Stub implementation.
    // TODO: Handle overflow flag.
    // NOTE: 535507D4 (Raiden Fighters Aces) never seems to rely on this
    //   behavior either, despite OE being set.
  }
  return 0;
}

Special Cases & Edge Conditions

• Carry-in is consumed and carry-out is produced. addex is the middle link of a multi-word add chain seeded by addcx: RT ← RA + RB + XER[CA], then XER[CA] ← carry_out.
• Carry-out detection handles both edges. Canary's AddWithCarryDidCarry (after PearPC) sets CA if (a + b) <u a or (a + b + ca) <u ca — the second clause covers the case where adding the carry-in alone wraps (RB == ~0 && CA == 1), which the naive result < ra test misses. ⚠️ It works on the low 32 bits of RA/RB, so CA is the 32-bit carry, not the 64-bit one.
• No trap on signed overflow. addeo/addeo. only update XER[OV] and sticky XER[SO]. Canary's OE branch is an empty stub ("TODO: Handle overflow flag"), so OV is never set — unlike addme/addze, CA is still stored.
• 64-bit CR update on Xenon, 32-bit in Canary. f.UpdateCR(0, v) truncates v to INT32 before the signed compare with zero. For multi-word adds whose final word is the high 32 bits of a 64-bit value, this distinction matters; see addx.
• XER[CA] must be initialised by an earlier addcx, subfcx, or mtspr to XER. Reading stale CA from an unrelated instruction is the most common bug in hand-written multi-word arithmetic.
• XER[SO] is sticky until cleared by mcrxr; Rc=1 copies it into CR0[SO].

Related Instructions

• addcx — seeds the carry chain (no CA read, sets CA).
• addmex, addzex — terminate the chain (RA + −1 + CA, RA + 0 + CA).
• addx — plain add without XER[CA].
• subfex — dual: ~RA + RB + XER[CA], used for multi-word subtract.
• addic / addicx — immediate carrying adds that initialise a chain.

IBM Reference

• AIX 7.3 — adde (Add Extended)
• PowerISA v2.07B, Book I, §3.3.8 — defines the RA + RB + CA carry-chain composition.