Sylpheed/tools/ppc-manual/alu/rldicrx.md

rldicrx — Rotate Left Doubleword Immediate then Clear Right

Category: Integer ALU · Form: MD · Opcode: 0x78000004

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
rldicr	rldicrx	—	Rotate Left Doubleword Immediate then Clear Right
rldicr.	rldicrx	Rc=1	Rotate Left Doubleword Immediate then Clear Right

Syntax

rldicr[Rc] [RA], [RS], [SH], [ME]

Encoding

rldicrx — form MD

• Opcode word: 0x78000004
• Primary opcode (bits 0–5): 30
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (30)
6–10	RS	source GPR
11–15	RA	destination GPR
16–20	sh	shift amount low 5 bits
21–26	mb/me	6-bit mask field (swapped halves)
27–29	XO	extended opcode
30	sh5	shift amount high bit
31	Rc	record-form flag

Operands

Field	Role	Description
RS	rldicrx: read	Source GPR (alias for RD in some stores).
SH	rldicrx: read	Shift amount.
ME	rldicrx: read	Mask end bit.
RA	rldicrx: write	Source GPR (r0–r31).
CR	rldicrx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

rldicrx

• Reads (always): RS, SH, ME
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): CR

Status-Register Effects

• rldicrx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

rldicrx

• Canary XML: tools/ppc-instructions.xml — search for mnem="rldicrx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_alu.cc:957
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:207
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:844

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_rldicrx(PPCHIRBuilder& f, const InstrData& i) {
  // n <- sh[5] || sh[0:4]
  // r <- ROTL64((RS), n)
  // e <- me[5] || me[0:4]
  // m <- MASK(0, e)
  // RA <- r & m
  uint32_t sh = (i.MD.SH5 << 5) | i.MD.SH;
  uint32_t mb = (i.MD.MB5 << 5) | i.MD.MB;
  uint64_t m = XEMASK(0, mb);
  Value* v = f.LoadGPR(i.MD.RT);
  if (mb == 63 - sh) {
    // sldi ==  rldicr ra,rs,n,63-n
    v = f.Shl(v, int8_t(sh));
  } else {
    if (sh) {
      v = f.RotateLeft(v, f.LoadConstantInt8(sh));
    }
    if (m != 0xFFFFFFFFFFFFFFFF) {
      v = f.And(v, f.LoadConstantUint64(m));
    }
  }
  f.StoreGPR(i.MD.RA, v);
  if (i.MD.Rc) {
    f.UpdateCR(0, v);
  }
  return 0;
}

Special Cases & Edge Conditions

• RA ← ROTL64(RS, SH) & MASK(0, ME). Rotate left by SH, then clear bits ME+1..63.
• Common simplified mnemonics:
  • sldi RA, RS, n ≡ rldicr RA, RS, n, 63-n — logical left shift by n.
  • clrrdi RA, RS, n ≡ rldicr RA, RS, 0, 63-n — clear low n bits.
  • extldi RA, RS, n, b ≡ rldicr RA, RS, b, n-1 — extract n bits from position b left-aligned.
• SH is 6 bits, immediate. Same instr.sh64() decode as the rest of the family.
• ME is 6 bits, split-encoded. Canary reads it through the MD form's MB/MB5 fields — the slot MB occupies in sister instructions; the operation just interprets it as the right edge.
• Rc=1 CR0 update is 32-bit in Canary (f.UpdateCR(0, v)). When ME == 63 − SH, Canary emits a plain Shl by SH — the sldi idiom — instead of rotate-and-mask.
• No XER effect.
• Heavily emitted by 64-bit code generators for left-shift-and-clear sequences. Recognising the simplified mnemonics aids disassembly.

Related Instructions

• rldiclx — clear-left counterpart (MASK(MB, 63)).
• rldicx — clear both ends.
• rldcrx — register-shift version.
• rldimix — insert under mask.
• rlwinmx — 32-bit cousin.
• sldi, clrrdi, extldi (simplified mnemonics).

IBM Reference

• AIX 7.3 — rldicr (Rotate Left Doubleword Immediate then Clear Right)