Sylpheed/tools/ppc-manual/alu/rldcrx.md

rldcrx — Rotate Left Doubleword then Clear Right

Category: Integer ALU · Form: MDS · Opcode: 0x78000012

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
rldcr	rldcrx	—	Rotate Left Doubleword then Clear Right
rldcr.	rldcrx	Rc=1	Rotate Left Doubleword then Clear Right

Syntax

rldcr[Rc] [RA], [RS], [RB], [ME]

Encoding

rldcrx — form MDS

• Opcode word: 0x78000012
• Primary opcode (bits 0–5): 30
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (30)
6–10	RS	source GPR
11–15	RA	destination GPR
16–20	RB	source B GPR
21–26	mb/me	6-bit mask field (swapped halves)
27–30	XO	extended opcode
31	Rc	record-form flag

Operands

Field	Role	Description
RS	rldcrx: read	Source GPR (alias for RD in some stores).
RB	rldcrx: read	Source GPR.
ME	rldcrx: read	Mask end bit.
RA	rldcrx: write	Source GPR (r0–r31).
CR	rldcrx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

rldcrx

• Reads (always): RS, RB, ME
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): CR

Status-Register Effects

• rldcrx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

rldcrx

• Canary XML: tools/ppc-instructions.xml — search for mnem="rldcrx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_alu.cc:881
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:205
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:849

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_rldcrx(PPCHIRBuilder& f, const InstrData& i) {
  // n <- rB[58:63]
  // r <- ROTL[64](rS, n)
  // b <- mb[5] || mb[0:4]
  // m <- MASK(0, b)
  // rA <- r & m
  Value* n = f.And(f.Truncate(f.LoadGPR(i.MDS.RB), INT8_TYPE),
                   f.LoadConstantInt8(0x3F));

  uint32_t mb = (i.MDS.MB5 << 5) | i.MDS.MB;
  uint64_t m = XEMASK(0, mb);
  Value* v = f.LoadGPR(i.MDS.RT);

  v = f.RotateLeft(v, n);
  if (m != 0xFFFFFFFFFFFFFFFF) {
    v = f.And(v, f.LoadConstantUint64(m));
  }

  f.StoreGPR(i.MDS.RA, v);
  if (i.MDS.Rc) {
    f.UpdateCR(0, v);
  }
  return 0;
}

Special Cases & Edge Conditions

• RA ← ROTL64(RS, RB[58:63]) & MASK(0, ME). Rotate RS left by RB & 0x3F, then clear bits to the right of ME — keep bits 0..ME, force bits ME+1..63 to zero.
• Shift from register. Same as rldclx: only the low 6 bits of RB count.
• ME is a split 6-bit field. Encoded exactly like MB in rldclx — Canary even reads it from the same InstrData.MDS fields as (MB5 << 5) | MB — and applied as the mask end, XEMASK(0, ME).
• Mask generation. rld_mask_right(ME) = ~((1 << (63 - ME)) - 1) keeping bits 0..ME. When ME = 63 the mask is all ones; when ME = 0 only bit 0 survives.
• Rc=1 CR0 update is 32-bit in Canary (f.UpdateCR(0, v)).
• No XER effect.
• Useful for left-shift with arbitrary discard. rldcr RA, RS, RB, 63 - n is functionally close to a left-shift-and-mask sequence, with the rotate variant additionally allowing wrap-around.

Related Instructions

• rldclx — sister: clear left instead of right.
• rldicrx — immediate-shift form.
• rldicx, rldiclx, rldimix — full immediate rotate-and-mask family.
• sldx — plain 64-bit logical left shift (often a strength-reduced equivalent).

IBM Reference

• AIX 7.3 — rldcr (Rotate Left Doubleword then Clear Right)