Sylpheed/tools/ppc-manual/alu/srwx.md

srwx — Shift Right Word

Category: Integer ALU · Form: X · Opcode: 0x7c000430

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
srw	srwx	—	Shift Right Word
srw.	srwx	Rc=1	Shift Right Word

Syntax

srw[Rc] [RA], [RS], [RB]

Encoding

srwx — form X

• Opcode word: 0x7c000430
• Primary opcode (bits 0–5): 31
• Extended opcode: 536
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RS	srwx: read	Source GPR (alias for RD in some stores).
RB	srwx: read	Source GPR.
RA	srwx: write	Source GPR (r0–r31).
CR	srwx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

srwx

• Reads (always): RS, RB
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): CR

Status-Register Effects

• srwx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

n <- (RB)[58:63]
RA <- ((RS)[32:63] >> n)  zero-extended   if n < 32 else 0

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

srwx

• Canary XML: tools/ppc-instructions.xml — search for mnem="srwx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_alu.cc:1180
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:223
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:935

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_srwx(PPCHIRBuilder& f, const InstrData& i) {
  // n <- (RB)[59:63]
  // r <- ROTL32((RS)[32:63], 64-n)
  // if (RB)[58] = 0 then
  //   m <- MASK(n+32, 63)
  // else
  //   m <- i64.0
  // RA <- r & m
  Value* sh =
      f.And(f.Truncate(f.LoadGPR(i.X.RB), INT8_TYPE), f.LoadConstantInt8(0x3F));
  Value* v =
      f.Select(f.IsTrue(f.And(sh, f.LoadConstantInt8(0x20))), f.LoadZeroInt32(),
               f.Shr(f.Truncate(f.LoadGPR(i.X.RT), INT32_TYPE), sh));
  v = f.ZeroExtend(v, INT64_TYPE);
  f.StoreGPR(i.X.RA, v);
  if (i.X.Rc) {
    f.UpdateCR(0, v);
  }
  return 0;
}

Special Cases & Edge Conditions

• 32-bit logical right shift, zero-extended to 64. RA ← (u32)RS >> (RB & 0x3F) if count < 32, else RA = 0. The high 32 bits of RA are always zero.
• Shift count is 6 bits, RB[58:63]. Counts [32, 63] produce zero (not RS >> (count mod 32)): Canary emits Select(sh & 0x20, 0, RS[32:63] >> sh) and zero-extends the result.
• No XER[CA] produced. For arithmetic shift with XER[CA] use srawx.
• Rc=1 CR0 update truncates to 32 bits in Canary (f.UpdateCR(0, v)). After a non-zero shift the 32-bit result's top bit is 0, so both give EQ or GT. With a count of 0 the result is RS[32:63] itself: if its top bit is set, spec (high word zero) says GT and Canary says LT.
• No OE bit.
• srwi simplified mnemonic uses rlwinmx, not this instruction. srw is for runtime-variable counts.

Related Instructions

• srdx — 64-bit logical right shift.
• srawx, srawix — 32-bit arithmetic right.
• slwx — 32-bit left shift.
• rlwinmx — srwi immediate expansion.

IBM Reference

• AIX 7.3 — srw (Shift Right Word)