Sylpheed/tools/ppc-manual/alu/srdx.md

srdx — Shift Right Doubleword

Category: Integer ALU · Form: X · Opcode: 0x7c000436

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
srd	srdx	—	Shift Right Doubleword
srd.	srdx	Rc=1	Shift Right Doubleword

Syntax

srd[Rc] [RA], [RS], [RB]

Encoding

srdx — form X

• Opcode word: 0x7c000436
• Primary opcode (bits 0–5): 31
• Extended opcode: 539
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RS	srdx: read	Source GPR (alias for RD in some stores).
RB	srdx: read	Source GPR.
RA	srdx: write	Source GPR (r0–r31).
CR	srdx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

srdx

• Reads (always): RS, RB
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): CR

Status-Register Effects

• srdx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

n <- (RB)[57:63]
RA <- ((RS) >> n)                       if n < 64 else 0

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

srdx

• Canary XML: tools/ppc-instructions.xml — search for mnem="srdx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_alu.cc:1161
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:222
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:936

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_srdx(PPCHIRBuilder& f, const InstrData& i) {
  // n <- (RB)[58:63]
  // r <- ROTL64((RS), 64-n)
  // if (RB)[57] = 0 then
  //   m <- MASK(n, 63)
  // else
  //   m <- i64.0
  // RA <- r & m
  Value* sh =
      f.And(f.Truncate(f.LoadGPR(i.X.RB), INT8_TYPE), f.LoadConstantInt8(0x7F));
  Value* v = f.Select(f.IsTrue(f.And(sh, f.LoadConstantInt8(0x40))),
                      f.LoadZeroInt64(), f.Shr(f.LoadGPR(i.X.RT), sh));
  f.StoreGPR(i.X.RA, v);
  if (i.X.Rc) {
    f.UpdateCR(0, v);
  }
  return 0;
}

Special Cases & Edge Conditions

• 64-bit logical right shift. RA ← RS >> (RB & 0x7F) if the count is < 64, else RA = 0. Bits shifted in from the high end are zero (no sign extension).
• Shift count is 7 bits (RB[57:63]). Counts 64..127 produce zero, not RS >> (count mod 64). Canary emits Select(sh & 0x40, 0, RS >> sh) with sh = RB & 0x7F.
• No XER[CA] produced. This is the logical right shift; for arithmetic shift with XER[CA] use sradx.
• Rc=1 CR0 update is 32-bit in Canary (f.UpdateCR(0, v)). Per spec, any non-zero count clears the top bit, so CR0 is EQ or GT (a count of 0 leaves RS itself, which may be negative). Canary compares only the low word, whose most-significant bit can still be set, so it can report LT where spec says GT.
• No OE bit.
• The srdi simplified mnemonic uses rldiclx instead — rldicl rA, rS, 64-n, n — because it can be combined with masking. srd is for runtime-variable counts.

Related Instructions

• srwx — 32-bit logical right shift.
• sradx, sradix — 64-bit arithmetic right.
• sldx — 64-bit left shift.
• rldiclx — srdi immediate-shift expansion.

IBM Reference

• AIX 7.3 — srd (Shift Right Doubleword)