f3c512f2ab
The hand-written parts of the manual still described how the retired xenia-rs interpreter behaved: its snapshots, Rust casts and helpers. Each of those 490 statements is now either restated as what Canary's emitters and x64 backend actually do (at the pinned canary_experimental commit), or dropped where it only made sense for xenia-rs. Checking them turned up claims that were wrong, not just outdated: - VSCR[SAT] is never modelled in Canary (DID_SATURATE is a stub and mfvscr cannot see it); the pages said saturating ops set it stickily. - Canary does not implement lswi/lswx/stswi/stswx, dcbi, mtfsb0/mtfsb1, vmsum*, vmhaddshs, vupkhpx/vupklpx, and most SPRs; pages described them as working. - Traps evaluate TO in Canary; stvebx/stvehx/stvewx store one element, not 16 bytes; mtmsrd writes only EE; fres/frsqrte/vrsqrtefp precision claims and the stfs "rounds under RN / sets FPSCR" claim contradicted the spec. - Reservations are a 64 KiB block bitmap plus a value compare, not per-address tracking. Claims that neither Canary's source nor a public spec settles are marked unverified (NI at boot, vmaddcfp128 operand order, estimate bit-exactness). Generated regions are untouched; re-running the generator changes nothing. Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
139 lines
5.8 KiB
Markdown
139 lines
5.8 KiB
Markdown
# `crand` — Condition Register AND
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> **Category:** [Control / CR / SPR](../categories/control.md) · **Form:** [XL](../forms/XL.md) · **Opcode:** `0x4c000202`
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<!-- GENERATED: BEGIN -->
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## Assembler Mnemonics
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| Mnemonic | XML entry | Flags | Description |
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| --- | --- | --- | --- |
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| `crand` | `crand` | — | Condition Register AND |
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## Syntax
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```asm
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crand [CRBD], [CRBA], [CRBB]
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```
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## Encoding
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### `crand` — form `XL`
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- **Opcode word:** `0x4c000202`
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- **Primary opcode (bits 0–5):** `19`
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- **Extended opcode:** `257`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode (19) |
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| 6–10 | `BT/BO` | target / branch options |
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| 11–15 | `BA/BI` | source A / CR bit to test |
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| 16–20 | `BB` | source B |
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| 21–30 | `XO` | extended opcode (10 bits) |
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| 31 | `LK` | link flag |
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## Operands
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| Field | Role | Description |
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| --- | --- | --- |
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| `CRBA` | crand: read | CR source bit A (0–31). |
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| `CRBB` | crand: read | CR source bit B (0–31). |
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| `CRBD` | crand: write | CR destination bit (0–31). |
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## Register Effects
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### `crand`
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- **Reads (always):** `CRBA`, `CRBB`
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- **Reads (conditional):** _none_
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- **Writes (always):** `CRBD`
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- **Writes (conditional):** _none_
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## Status-Register Effects
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_No condition-register or status-register effects._
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## Operation (pseudocode)
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```
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; No hand-written pseudocode for this instruction yet.
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; The authoritative semantics are the Canary emitter snapshot under
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; Implementation References; about half of Canary's emitters open
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; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
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; Every side effect is also enumerated in the Register Effects and
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; Status-Register Effects tables above.
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```
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## C Translation Example
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```c
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/* No hand-written C yet. Translate the Canary emitter snapshot */
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/* under Implementation References; its HIR maps directly: */
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/* f.LoadGPR(n) / f.StoreGPR(n, v) -> r[n] / r[n] = v */
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/* f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n] */
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/* f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters */
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/* wrap them in f.ByteSwap for the big-endian guest value */
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/* f.UpdateCR(n, v) -> CR field n from v's LOW 32 BITS vs 0 */
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/* f.LoadCA / f.StoreCA -> xer.CA; f.StoreSAT -> vscr.SAT */
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/* i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands */
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/* The Register Effects and Status-Register Effects tables above */
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/* enumerate every side effect a faithful translation must emit. */
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```
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## Implementation References
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**`crand`**
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- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="crand"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
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- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_control.cc:352`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_control.cc#L352)
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- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:35`](../../../crates/sylpheed-ppc/src/opcode.rs#L35)
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- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:832`](../../../crates/sylpheed-ppc/src/decoder.rs#L832)
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<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>
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```cpp
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int InstrEmit_crand(PPCHIRBuilder& f, const InstrData& i) {
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// CR[bt] <- CR[ba] & CR[bb] bt=bo, ba=bi, bb=bb
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Value* ba = f.LoadCRField(i.XL.BI >> 2, i.XL.BI & 3);
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Value* bb = f.LoadCRField(i.XL.BB >> 2, i.XL.BB & 3);
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Value* bt = f.And(ba, bb);
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f.StoreCRField(i.XL.BO >> 2, i.XL.BO & 3, bt);
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return 0;
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}
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```
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</details>
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<!-- GENERATED: END -->
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## Special Cases & Edge Conditions
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- **Bit-level granularity.** All eight CR-logical instructions operate on **single CR bits**, not whole 4-bit fields. `CRBD`, `CRBA`, `CRBB` are 5-bit absolute indices into the 32-bit CR register: `BI = 4·field + bit-within-field`, where bit 0 = LT, 1 = GT, 2 = EQ, 3 = SO.
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- **Operation.** `CR[CRBD] ← CR[CRBA] AND CR[CRBB]`. All other CR bits are preserved.
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- **Same-source / same-destination quirks.** Identical sources and destinations are legal: `crand 6, 6, 6` is a NOP-style "force CR bit 6 to itself"; `crand bt, bt, bt` reads-then-writes the same bit (no observable change). Compilers exploit `crxor BT,BT,BT` ("clear bit") and `creqv BT,BT,BT` ("set bit") for similar tricks — see those pages.
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- **Combining branch conditions.** The classic use: synthesise complex branch conditions from multiple compare results. Example: `cmpw cr0, r3, r4; cmpw cr1, r5, r6; crand 4*cr0+2, 4*cr0+2, 4*cr1+2; beq cr0, label` branches if `r3==r4 AND r5==r6` using a single conditional branch.
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- **No `Rc` / `OE`.** XL-form CR-logical ops never set CR0 or XER; they only update the named CR bit.
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- **Not synchronising.** Pure data-flow on CR; freely reorderable.
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- **Canary status.** Canary's `InstrEmit_crand` emits a host AND of the two CR bits.
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## Related Instructions
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- [`crandc`](crandc.md) — AND with complement: `CR[BT] ← CR[BA] AND ¬CR[BB]`.
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- [`cror`](cror.md), [`crorc`](crorc.md) — OR / OR-with-complement.
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- [`crnand`](crnand.md), [`crnor`](crnor.md) — negated AND / OR.
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- [`crxor`](crxor.md), [`creqv`](creqv.md) — XOR and equivalence (XNOR).
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- [`mcrf`](mcrf.md) — copy a whole 4-bit CR field.
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- [`bcx`](../branch/bcx.md) consumers — the typical reason to compute composite CR bits.
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### Simplified Mnemonics
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- `crmove BT, BA` ≡ `cror BT, BA, BA` (use `cror`, not `crand`).
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- `crset BT` ≡ `creqv BT, BT, BT` (set to 1).
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- `crclr BT` ≡ `crxor BT, BT, BT` (clear to 0).
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`crand` itself has no dedicated simplified mnemonic.
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## IBM Reference
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- [AIX 7.3 — `crand` (Condition Register AND)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-crand-condition-register-instruction)
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- [AIX 7.3 — Condition register simplified mnemonics](https://www.ibm.com/docs/en/aix/7.3.0?topic=mnemonics-condition-register-logical-simplified)
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