f3c512f2ab
The hand-written parts of the manual still described how the retired xenia-rs interpreter behaved: its snapshots, Rust casts and helpers. Each of those 490 statements is now either restated as what Canary's emitters and x64 backend actually do (at the pinned canary_experimental commit), or dropped where it only made sense for xenia-rs. Checking them turned up claims that were wrong, not just outdated: - VSCR[SAT] is never modelled in Canary (DID_SATURATE is a stub and mfvscr cannot see it); the pages said saturating ops set it stickily. - Canary does not implement lswi/lswx/stswi/stswx, dcbi, mtfsb0/mtfsb1, vmsum*, vmhaddshs, vupkhpx/vupklpx, and most SPRs; pages described them as working. - Traps evaluate TO in Canary; stvebx/stvehx/stvewx store one element, not 16 bytes; mtmsrd writes only EE; fres/frsqrte/vrsqrtefp precision claims and the stfs "rounds under RN / sets FPSCR" claim contradicted the spec. - Reservations are a 64 KiB block bitmap plus a value compare, not per-address tracking. Claims that neither Canary's source nor a public spec settles are marked unverified (NI at boot, vmaddcfp128 operand order, estimate bit-exactness). Generated regions are untouched; re-running the generator changes nothing. Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
132 lines
6.0 KiB
Markdown
132 lines
6.0 KiB
Markdown
# `fmsubsx` — Floating Multiply-Subtract Single
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> **Category:** [Floating-Point](../categories/fpu.md) · **Form:** [A](../forms/A.md) · **Opcode:** `0xec000038`
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<!-- GENERATED: BEGIN -->
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## Assembler Mnemonics
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| Mnemonic | XML entry | Flags | Description |
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| --- | --- | --- | --- |
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| `fmsubs` | `fmsubsx` | — | Floating Multiply-Subtract Single |
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| `fmsubs.` | `fmsubsx` | Rc=1 | Floating Multiply-Subtract Single |
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## Syntax
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```asm
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fmsubs[Rc] [FD], [FA], [FC], [FB]
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```
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## Encoding
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### `fmsubsx` — form `A`
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- **Opcode word:** `0xec000038`
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- **Primary opcode (bits 0–5):** `59`
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- **Extended opcode:** `28`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode (59 or 63) |
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| 6–10 | `FRT` | destination FPR |
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| 11–15 | `FRA` | source A FPR |
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| 16–20 | `FRB` | source B FPR |
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| 21–25 | `FRC` | source C FPR (multiplier for madd-style ops) |
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| 26–30 | `XO` | extended opcode (5 bits) |
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| 31 | `Rc` | record-form flag (updates CR1) |
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## Operands
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| Field | Role | Description |
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| --- | --- | --- |
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| `FA` | fmsubsx: read | Source A floating-point register (`fr0`–`fr31`). |
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| `FC` | fmsubsx: read | Source C floating-point register (for madd-style ops). |
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| `FB` | fmsubsx: read | Source B floating-point register. |
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| `FD` | fmsubsx: write | Destination floating-point register. |
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| `CR` | fmsubsx: write (conditional) | Condition-register update. When `Rc=1`, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result. |
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| `FPSCR` | fmsubsx: write | Floating-Point Status and Control Register. |
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## Register Effects
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### `fmsubsx`
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- **Reads (always):** `FA`, `FC`, `FB`
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- **Reads (conditional):** _none_
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- **Writes (always):** `FD`, `FPSCR`
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- **Writes (conditional):** `CR`
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## Status-Register Effects
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- `fmsubsx`: **CR1** ← FPSCR[FX, FEX, VX, OX] when `Rc=1`.; **FPSCR** updated per IEEE-754 flags (FX, FEX, FPRF, FR, FI, exceptions).
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## Operation (pseudocode)
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```
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; No hand-written pseudocode for this instruction yet.
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; The authoritative semantics are the Canary emitter snapshot under
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; Implementation References; about half of Canary's emitters open
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; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
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; Every side effect is also enumerated in the Register Effects and
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; Status-Register Effects tables above.
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```
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## C Translation Example
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```c
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/* No hand-written C yet. Translate the Canary emitter snapshot */
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/* under Implementation References; its HIR maps directly: */
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/* f.LoadGPR(n) / f.StoreGPR(n, v) -> r[n] / r[n] = v */
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/* f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n] */
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/* f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters */
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/* wrap them in f.ByteSwap for the big-endian guest value */
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/* f.UpdateCR(n, v) -> CR field n from v's LOW 32 BITS vs 0 */
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/* f.LoadCA / f.StoreCA -> xer.CA; f.StoreSAT -> vscr.SAT */
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/* i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands */
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/* The Register Effects and Status-Register Effects tables above */
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/* enumerate every side effect a faithful translation must emit. */
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```
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## Implementation References
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**`fmsubsx`**
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- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="fmsubsx"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
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- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_fpu.cc:209`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_fpu.cc#L209)
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- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:79`](../../../crates/sylpheed-ppc/src/opcode.rs#L79)
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- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:507`](../../../crates/sylpheed-ppc/src/decoder.rs#L507)
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<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>
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```cpp
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int InstrEmit_fmsubsx(PPCHIRBuilder& f, const InstrData& i) {
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return InstrEmit_fmsub(f, i, true);
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}
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```
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</details>
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<!-- GENERATED: END -->
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## Special Cases & Edge Conditions
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- **Single rounding step then round-to-single.** PowerISA computes `(FRA × FRC) − FRB` exactly and rounds once to binary32. Canary rounds twice: `MulSub` in binary64 (`vfmsub213sd` on FMA3 hosts, `vmulsd` + `vsubsd` otherwise), then `ToSingle`.
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- **Operand order.** Assembler: `FD, FA, FC, FB`. The multiplier `FRC` precedes the addend `FRB`.
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- **Invalid operations.** `0×∞ − finite` → `VXIMZ`; `(±∞×x) − ±∞` (same sign) → `VXISI`. Quiet NaN result with `FPSCR[VX, FX]`.
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- **FPSCR side effects.** Hardware updates `FPRF`, `FR`, `FI`, `FX`, `OX`, `UX`, `XX`, `VXIMZ`, `VXISI`, `VXSNAN`. Canary does not (`UpdateFPSCR` is a stub).
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- **`Rc=1` (`fmsubs.`)** copies `FPSCR[FX, FEX, VX, OX]` into CR1.
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- **NaN propagation.** Quiet-NaN result for any NaN operand; signalling NaNs are quietened.
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- **Single-precision overflow** of the final rounded result returns ±∞ and sets `OX`/`XX`/`FX`.
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- **Use case.** Newton-Raphson refinement of `fres`: `x_new = x*(2 - d*x)` decomposes to a `fmsubs`/`fnmsubs` pair. Also common in residual-correction loops.
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- **Denormal flush.** That Xenon boots with `FPSCR[NI]=1` is unverified. Canary starts every guest thread in IEEE mode (MXCSR `0x1F80`; its init comment flags the startup state as unchecked) and turns on the host's flush-to-zero (`MXCSR.FZ`) only when the guest sets `NI` through `mtfsf`/`mtfsfi`.
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## Related Instructions
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- [`fmsubx`](fmsubx.md) — double-precision sibling.
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- [`fmaddsx`](fmaddsx.md), [`fnmaddsx`](fnmaddsx.md), [`fnmsubsx`](fnmsubsx.md) — other single-precision fused-multiply variants.
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- [`fmulsx`](fmulsx.md), [`fsubsx`](fsubsx.md) — non-fused decomposition.
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- [`fresx`](fresx.md), [`frsqrtex`](frsqrtex.md) — reciprocal helpers refined by `fmsubs`/`fnmsubs`.
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- [`frspx`](frspx.md) — explicit double→single rounding.
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## IBM Reference
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- [AIX 7.3 — `fmsubs` (Floating Multiply-Subtract Single)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-fmsubs-floating-multiply-subtract-single-instruction)
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- [PowerISA v2.07B, Book I, Chapter 4 — Floating-Point Processor](https://openpowerfoundation.org/specifications/isa/).
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