Sylpheed/tools/ppc-manual/memory/lvxl.md

lvxl — Load Vector Indexed LRU

Category: Memory · Form: X · Opcode: 0x7c0002ce

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
lvxl	lvxl	—	Load Vector Indexed LRU
lvxl128	lvxl128	—	Load Vector Indexed LRU 128

Syntax

lvslx [VD], [RA0], [RB]
lvxl128 [VD], [RA0], [RB]

Encoding

lvxl — form X

• Opcode word: 0x7c0002ce
• Primary opcode (bits 0–5): 31
• Extended opcode: 359
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

lvxl128 — form VX128_1

• Opcode word: 0x100002c3
• Primary opcode (bits 0–5): 4
• Extended opcode: 707
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VD128l	destination low 5 bits
11–15	RA	address register
16–20	RB	offset register
21–27	XO	extended opcode
28–29	VD128h	destination high 2 bits
30–31	—	reserved

Operands

Field	Role	Description
RA0	lvxl: read; lvxl128: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.
RB	lvxl: read; lvxl128: read	Source GPR.
VD	lvxl: write; lvxl128: write	Destination vector register.

Register Effects

lvxl

• Reads (always): RA0, RB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

lvxl128

• Reads (always): RA0, RB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

lvxl

• Canary XML: tools/ppc-instructions.xml — search for mnem="lvxl"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:145
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:154
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:917

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_lvxl(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_lvx(f, i);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:139) ──
int InstrEmit_lvx(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_lvx_(f, i, i.X.RT, i.X.RA, i.X.RB);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:133) ──
int InstrEmit_lvx_(PPCHIRBuilder& f, const InstrData& i, uint32_t vd,
                   uint32_t ra, uint32_t rb) {
  Value* ea = f.And(CalculateEA_0(f, ra, rb), f.LoadConstantInt64(~0xFull));
  f.StoreVR(vd, f.ByteSwap(f.Load(ea, VEC128_TYPE)));
  return 0;
}

lvxl128

• Canary XML: tools/ppc-instructions.xml — search for mnem="lvxl128"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:148
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:155
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:533

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_lvxl128(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_lvx128(f, i);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:142) ──
int InstrEmit_lvx128(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_lvx_(f, i, VX128_1_VD128, i.VX128_1.RA, i.VX128_1.RB);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:133) ──
int InstrEmit_lvx_(PPCHIRBuilder& f, const InstrData& i, uint32_t vd,
                   uint32_t ra, uint32_t rb) {
  Value* ea = f.And(CalculateEA_0(f, ra, rb), f.LoadConstantInt64(~0xFull));
  f.StoreVR(vd, f.ByteSwap(f.Load(ea, VEC128_TYPE)));
  return 0;
}

Special Cases & Edge Conditions

• Same data effect as lvx, but with cache hint. Loads 16 bytes from EA & ~0xF into VD. The l suffix signals to the cache hardware that the line is least-recently-used — a hint that the line will not be reused soon, allowing the cache to evict it preferentially under pressure. Useful in streaming reads (e.g. once-through vertex transforms, decode passes).
• Hint ignored under emulation. Canary's lvxl simply calls its lvx emitter, so the functional behaviour is identical to lvx — only real hardware acts on the hint.
• Alignment is forced, not checked. Like lvx, the low four bits of EA are masked. Unaligned EA silently rounds down to the 16-byte boundary.
• Big-endian lane layout. Byte at the aligned base goes into lane 0; byte at base+15 into lane 15.
• RA0 semantics. RA = 0 selects literal zero.
• No update form. lvxl has no u-suffix variant.
• VMX128 sibling (lvxl128). Identical semantics; the only difference is the operand encoding using the split-field 7-bit register index addressing v0..v127. Canary's lvxl128 calls lvx128, which decodes the 7-bit index and shares lvx's body.
• Note: assembler typo. The Syntax block above shows lvslx for the non-128 variant — that is a transcription artefact of the source XML. The real mnemonic is lvxl.

Related Instructions

• lvx, lvx128 — same load without the LRU hint.
• stvxl, stvxl128 — symmetric "store last" variants.
• stvx — non-hint store.
• dcbt, dcbtst — explicit prefetch hints (the hint family).

IBM Reference

• AIX 7.3 — lvxl (Load Vector Indexed LRU)
• PowerISA v2.07B Book I "Vector Facility" for canonical hint semantics.