Sylpheed/tools/ppc-manual/memory/stvxl.md

stvxl — Store Vector Indexed LRU

Category: Memory · Form: X · Opcode: 0x7c0003ce

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
stvxl	stvxl	—	Store Vector Indexed LRU
stvxl128	stvxl128	—	Store Vector Indexed LRU 128

Syntax

stvxl [VS], [RA0], [RB]
stvxl128 [VS], [RA0], [RB]

Encoding

stvxl — form X

• Opcode word: 0x7c0003ce
• Primary opcode (bits 0–5): 31
• Extended opcode: 487
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

stvxl128 — form VX128_1

• Opcode word: 0x100003c3
• Primary opcode (bits 0–5): 4
• Extended opcode: 963
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VD128l	destination low 5 bits
11–15	RA	address register
16–20	RB	offset register
21–27	XO	extended opcode
28–29	VD128h	destination high 2 bits
30–31	—	reserved

Operands

Field	Role	Description
VS	stvxl: read; stvxl128: read	Source vector register (alias for VD on stores).
RA0	stvxl: read; stvxl128: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.
RB	stvxl: read; stvxl128: read	Source GPR.

Register Effects

stvxl

• Reads (always): VS, RA0, RB
• Reads (conditional): none
• Writes (always): none
• Writes (conditional): none

stvxl128

• Reads (always): VS, RA0, RB
• Reads (conditional): none
• Writes (always): none
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

stvxl

• Canary XML: tools/ppc-instructions.xml — search for mnem="stvxl"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:199
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:271
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:928

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_stvxl(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_stvx(f, i);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:193) ──
int InstrEmit_stvx(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_stvx_(f, i, i.X.RT, i.X.RA, i.X.RB);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:187) ──
int InstrEmit_stvx_(PPCHIRBuilder& f, const InstrData& i, uint32_t vd,
                    uint32_t ra, uint32_t rb) {
  Value* ea = f.And(CalculateEA_0(f, ra, rb), f.LoadConstantUint64(~0xFull));
  f.Store(ea, f.ByteSwap(f.LoadVR(vd)));
  return 0;
}

stvxl128

• Canary XML: tools/ppc-instructions.xml — search for mnem="stvxl128"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:202
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:272
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:534

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_stvxl128(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_stvx128(f, i);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:196) ──
int InstrEmit_stvx128(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_stvx_(f, i, VX128_1_VD128, i.VX128_1.RA, i.VX128_1.RB);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:187) ──
int InstrEmit_stvx_(PPCHIRBuilder& f, const InstrData& i, uint32_t vd,
                    uint32_t ra, uint32_t rb) {
  Value* ea = f.And(CalculateEA_0(f, ra, rb), f.LoadConstantUint64(~0xFull));
  f.Store(ea, f.ByteSwap(f.LoadVR(vd)));
  return 0;
}

Special Cases & Edge Conditions

• Same data effect as stvx, with LRU cache hint. Writes 16 bytes from VS at EA & ~0xF. The l suffix tells the cache the line is least-recently-used — useful for streaming output (e.g. one-pass writes to a render target the producer will not re-read).
• Hint ignored under emulation. Canary's stvxl simply calls its stvx emitter (and stvxl128 calls stvx128); it implements only the data side. Hardware uses the hint to choose write-allocate vs. write-streaming behaviour.
• Alignment is forced, not checked. Low four bits of EA are masked.
• Big-endian lane layout. Lane 0 of VS lands at the aligned base; lane 15 at base+15.
• RA0 semantics. RA = 0 selects literal zero.
• No update form.
• VMX128 sibling (stvxl128). Identical semantics; alternative operand encoding addressing v0..v127 via the split-field 7-bit register index.
• Common in render-target writes. Pair with dcbz128 to allocate-and-zero, then stvxl to commit each line of a streaming output buffer; the LRU hint frees cache for the next line.

Related Instructions

• stvx, stvx128 — non-hint variants.
• lvxl, lvxl128 — symmetric LRU loads.
• stvebx, stvehx, stvewx — single-element stores.
• stvlx, stvrx — store-left / store-right unaligned ops.

IBM Reference

• AIX 7.3 — stvxl (Store Vector Indexed Last)
• PowerISA v2.07B Book I "Vector Facility"; Microsoft Xbox 360 XDK for stvxl128.