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Sylpheed/tools/ppc-manual/memory/stb.md
sim f3c512f2ab docs(ppc-manual): check every xenia-rs claim against Canary's source 
The hand-written parts of the manual still described how the retired
xenia-rs interpreter behaved: its snapshots, Rust casts and helpers. Each of
those 490 statements is now either restated as what Canary's emitters and
x64 backend actually do (at the pinned canary_experimental commit), or
dropped where it only made sense for xenia-rs.

Checking them turned up claims that were wrong, not just outdated:

- VSCR[SAT] is never modelled in Canary (DID_SATURATE is a stub and mfvscr
  cannot see it); the pages said saturating ops set it stickily.
- Canary does not implement lswi/lswx/stswi/stswx, dcbi, mtfsb0/mtfsb1,
  vmsum*, vmhaddshs, vupkhpx/vupklpx, and most SPRs; pages described them
  as working.
- Traps evaluate TO in Canary; stvebx/stvehx/stvewx store one element, not
  16 bytes; mtmsrd writes only EE; fres/frsqrte/vrsqrtefp precision claims
  and the stfs "rounds under RN / sets FPSCR" claim contradicted the spec.
- Reservations are a 64 KiB block bitmap plus a value compare, not
  per-address tracking.

Claims that neither Canary's source nor a public spec settles are marked
unverified (NI at boot, vmaddcfp128 operand order, estimate bit-exactness).

Generated regions are untouched; re-running the generator changes nothing.

Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
2026-09-16 21:52:38 +02:00

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# `stb` — Store Byte
> **Category:** [Memory](../categories/memory.md) · **Form:** [D](../forms/D.md) · **Opcode:** `0x98000000`
<!-- GENERATED: BEGIN -->
## Assembler Mnemonics
| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `stb` | `stb` | — | Store Byte |
| `stbu` | `stbu` | — | Store Byte with Update |
| `stbux` | `stbux` | — | Store Byte with Update Indexed |
| `stbx` | `stbx` | — | Store Byte Indexed |
## Syntax
```asm
stb [RS], [d]([RA0])
stbu [RS], [d]([RA])
stbux [RS], [RA], [RB]
stbx [RS], [RA0], [RB]
```
## Encoding
### `stb` — form `D`
- **Opcode word:** `0x98000000`
- **Primary opcode (bits 0–5):** `38`
- **Extended opcode:** —
- **Synchronising:** no
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–10 | `RT` | destination GPR (or RS when storing) |
| 11–15 | `RA` | source GPR (0 ⇒ literal 0 for RA0 forms) |
| 16–31 | `D/SI/UI` | 16-bit signed or unsigned immediate |
### `stbu` — form `D`
- **Opcode word:** `0x9c000000`
- **Primary opcode (bits 0–5):** `39`
- **Extended opcode:** —
- **Synchronising:** no
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–10 | `RT` | destination GPR (or RS when storing) |
| 11–15 | `RA` | source GPR (0 ⇒ literal 0 for RA0 forms) |
| 16–31 | `D/SI/UI` | 16-bit signed or unsigned immediate |
### `stbux` — form `X`
- **Opcode word:** `0x7c0001ee`
- **Primary opcode (bits 0–5):** `31`
- **Extended opcode:** `247`
- **Synchronising:** no
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–10 | `RT/FRT/VRT` | destination |
| 11–15 | `RA/FRA/VRA` | source A |
| 16–20 | `RB/FRB/VRB` | source B |
| 21–30 | `XO` | extended opcode (10 bits) |
| 31 | `Rc` | record-form flag |
### `stbx` — form `X`
- **Opcode word:** `0x7c0001ae`
- **Primary opcode (bits 0–5):** `31`
- **Extended opcode:** `215`
- **Synchronising:** no
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–10 | `RT/FRT/VRT` | destination |
| 11–15 | `RA/FRA/VRA` | source A |
| 16–20 | `RB/FRB/VRB` | source B |
| 21–30 | `XO` | extended opcode (10 bits) |
| 31 | `Rc` | record-form flag |
## Operands
| Field | Role | Description |
| --- | --- | --- |
| `RS` | stb: read; stbu: read; stbux: read; stbx: read | Source GPR (alias for RD in some stores). |
| `RA0` | stb: read; stbx: read | Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, **not** `r0`. |
| `d` | stb: read; stbu: read | 16-bit signed displacement (`d`) added to the base address register. |
| `RA` | stbu: read; stbu: write; stbux: read; stbux: write | Source GPR (`r0`–`r31`). |
| `RB` | stbux: read; stbx: read | Source GPR. |
## Register Effects
### `stb`
- **Reads (always):** `RS`, `RA0`, `d`
- **Reads (conditional):** _none_
- **Writes (always):** _none_
- **Writes (conditional):** _none_
### `stbu`
- **Reads (always):** `RS`, `RA`, `d`
- **Reads (conditional):** _none_
- **Writes (always):** `RA`
- **Writes (conditional):** _none_
### `stbux`
- **Reads (always):** `RS`, `RA`, `RB`
- **Reads (conditional):** _none_
- **Writes (always):** `RA`
- **Writes (conditional):** _none_
### `stbx`
- **Reads (always):** `RS`, `RA0`, `RB`
- **Reads (conditional):** _none_
- **Writes (always):** _none_
- **Writes (conditional):** _none_
## Status-Register Effects
_No condition-register or status-register effects._
## Operation (pseudocode)
```
EA <- (RA|0) + EXTS(d)
MEM(EA, 1) <- (RS)[56:63]
```
## C Translation Example
```c
/* No hand-written C yet. Translate the Canary emitter snapshot */
/* under Implementation References; its HIR maps directly: */
/* f.LoadGPR(n) / f.StoreGPR(n, v) -> r[n] / r[n] = v */
/* f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n] */
/* f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters */
/* wrap them in f.ByteSwap for the big-endian guest value */
/* f.UpdateCR(n, v) -> CR field n from v's LOW 32 BITS vs 0 */
/* f.LoadCA / f.StoreCA -> xer.CA; f.StoreSAT -> vscr.SAT */
/* i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands */
/* The Register Effects and Status-Register Effects tables above */
/* enumerate every side effect a faithful translation must emit. */
```
## Implementation References
**`stb`**
- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="stb"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:404`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_memory.cc#L404)
- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:225`](../../../crates/sylpheed-ppc/src/opcode.rs#L225)
- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:476`](../../../crates/sylpheed-ppc/src/decoder.rs#L476)
<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>
```cpp
int InstrEmit_stb(PPCHIRBuilder& f, const InstrData& i) {
// if RA = 0 then
// b <- 0
// else
// b <- (RA)
// EA <- b + EXTS(D)
// MEM(EA, 1) <- (RS)[56:63]
Value* b;
if (i.D.RA == 0) {
b = f.LoadZeroInt64();
} else {
b = f.LoadGPR(i.D.RA);
}
Value* offset = f.LoadConstantInt64(XEEXTS16(i.D.DS));
f.StoreOffset(b, offset, f.Truncate(f.LoadGPR(i.D.RT), INT8_TYPE));
return 0;
}
```
</details>
**`stbu`**
- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="stbu"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:423`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_memory.cc#L423)
- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:226`](../../../crates/sylpheed-ppc/src/opcode.rs#L226)
- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:477`](../../../crates/sylpheed-ppc/src/decoder.rs#L477)
<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>
```cpp
int InstrEmit_stbu(PPCHIRBuilder& f, const InstrData& i) {
// EA <- (RA) + EXTS(D)
// MEM(EA, 1) <- (RS)[56:63]
// RA <- EA
Value* ea = CalculateEA_i(f, i.D.RA, XEEXTS16(i.D.DS));
f.Store(ea, f.Truncate(f.LoadGPR(i.D.RT), INT8_TYPE));
StoreEA(f, i.D.RA, ea);
return 0;
}
```
</details>
**`stbux`**
- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="stbux"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:433`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_memory.cc#L433)
- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:227`](../../../crates/sylpheed-ppc/src/opcode.rs#L227)
- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:908`](../../../crates/sylpheed-ppc/src/decoder.rs#L908)
<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>
```cpp
int InstrEmit_stbux(PPCHIRBuilder& f, const InstrData& i) {
// EA <- (RA) + (RB)
// MEM(EA, 1) <- (RS)[56:63]
// RA <- EA
Value* ea = CalculateEA(f, i.X.RA, i.X.RB);
f.Store(ea, f.Truncate(f.LoadGPR(i.X.RT), INT8_TYPE));
StoreEA(f, i.X.RA, ea);
return 0;
}
```
</details>
**`stbx`**
- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="stbx"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:443`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_memory.cc#L443)
- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:228`](../../../crates/sylpheed-ppc/src/opcode.rs#L228)
- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:905`](../../../crates/sylpheed-ppc/src/decoder.rs#L905)
<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>
```cpp
int InstrEmit_stbx(PPCHIRBuilder& f, const InstrData& i) {
// if RA = 0 then
// b <- 0
// else
// b <- (RA)
// EA <- b + (RB)
// MEM(EA, 1) <- (RS)[56:63]
Value* ea = CalculateEA_0(f, i.X.RA, i.X.RB);
f.Store(ea, f.Truncate(f.LoadGPR(i.X.RT), INT8_TYPE));
return 0;
}
```
</details>
<!-- GENERATED: END -->
## Special Cases & Edge Conditions
- **Single-byte write.** Writes the low 8 bits of `RS` (`(RS)[56:63]` in IBM bit-numbering, equivalently `RS & 0xFF`) at `EA`. Canary stores `Truncate(RS, INT8)`, the GPR's low byte.
- **No endian concerns.** A single byte has no endianness — the byte at `EA` is the byte you wrote.
- **`RA0` (non-update forms).** `RA = 0` in `stb` and `stbx` selects literal zero as base — useful for absolute writes. Update forms `stbu` / `stbux` invoke `RA = 0` as an invalid form (no `RA = RT` collision since the source is `RS`, not `RT`).
- **Update-form post-write.** `stbu` / `stbux` write the computed `EA` back to `RA` after the store. The order is store-then-update; if `RA = RS` the store is unaffected (the store reads `RS` first), but the new `RA` value reflects `EA`, not the original `RS`.
- **No alignment requirement.** Byte stores are intrinsically aligned. Xenon never raises alignment exceptions for byte writes.
- **Common in string and packed-bool code.** Compilers emit `stb` for `char *` writes, packed boolean array updates, and small enum stores.
- **Cache effects.** A `stb` to a cold cache line triggers a cache-line read-allocate (load the whole line, modify one byte, mark dirty). When writing many bytes sequentially, prefer one [`stw`](stw.md) or [`stvx`](stvx.md), or pre-clear the line with [`dcbz128`](dcbz.md).
## Related Instructions
- [`sth`](sth.md), [`stw`](stw.md), [`std`](std.md) — wider stores (half / word / doubleword).
- [`lbz`](lbz.md) — corresponding load (no `lba` exists).
- [`stmw`](stmw.md), [`stswi`](stswi.md), [`stswx`](stswx.md) — multi-word / string stores for bulk transfer.
- [`stwbrx`](stwbrx.md), [`sthbrx`](sthbrx.md) — byte-reversed wider stores (no byte-equivalent needed).
## IBM Reference
- [AIX 7.3 — `stb` (Store Byte)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-stb-store-byte-instruction)
- [AIX 7.3 — `stbu` (Store Byte with Update)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-stbu-store-byte-update-instruction)
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