Sylpheed/tools/ppc-manual/vmx/vand.md

vand — Vector Logical AND

Category: VMX (Altivec) · Form: VX · Opcode: 0x10000404

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vand	vand	—	Vector Logical AND
vand128	vand128	—	Vector128 Logical AND

Syntax

vand [VD], [VA], [VB]
vand128 [VD], [VA], [VB]

Encoding

vand — form VX

• Opcode word: 0x10000404
• Primary opcode (bits 0–5): 4
• Extended opcode: 1028
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

vand128 — form VX128

• Opcode word: 0x14000210
• Primary opcode (bits 0–5): 5
• Extended opcode: 528
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4 or 5)
6–10	VD128l	destination low 5 bits
11–15	VA128l	source A low 5 bits
16–20	VB128l	source B low 5 bits
21	VA128H	source A high bit
22	—	reserved
23–25	VC	optional VC / XO sub-field
26	VA128h	source A middle bit
27	—	reserved
28–29	VD128h	destination high 2 bits
30–31	VB128h	source B high 2 bits

Operands

Field	Role	Description
VA	vand: read; vand128: read	Source A vector register.
VB	vand: read; vand128: read	Source B vector register.
VD	vand: write; vand128: write	Destination vector register.

Register Effects

vand

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

vand128

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vand

• Canary XML: tools/ppc-instructions.xml — search for mnem="vand"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:423
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:307
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:636

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vand(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_vand_(f, i.VX.VD, i.VX.VA, i.VX.VB);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:417) ──
int InstrEmit_vand_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb) {
  // VD <- (VA) & (VB)
  Value* v = f.And(f.LoadVR(va), f.LoadVR(vb));
  f.StoreVR(vd, v);
  return 0;
}

vand128

• Canary XML: tools/ppc-instructions.xml — search for mnem="vand128"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:426
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:308
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:734

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vand128(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_vand_(f, VX128_VD128, VX128_VA128, VX128_VB128);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:417) ──
int InstrEmit_vand_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb) {
  // VD <- (VA) & (VB)
  Value* v = f.And(f.LoadVR(va), f.LoadVR(vb));
  f.StoreVR(vd, v);
  return 0;
}

Special Cases & Edge Conditions

• Bitwise across the full 128 bits. VD = VA & VB. Lane width is irrelevant — the AND is bit-for-bit and there is no lane boundary. Canary emits one 128-bit And; any split (u8, u16, u32, u64) is observationally identical.
• No flags, no exceptions, no VSCR interaction. Pure combinational op; one of the cheapest VMX instructions.
• Common usage with compares. Compare ops produce per-lane all-ones / all-zero masks; vand with the mask selects the matching lanes (clearing the rest). For "select-by-mask" with a non-zero alternative use vsel instead.
• Idiom: clear lanes. vand VD, VD, vZero zeroes a register; in practice vxor VD, VD, VD is preferred since it doesn't need a zero-vector source.
• Aliasing legal. All three operands may overlap.
• VMX128 sibling (vand128). Identical semantics with the extended 128-register encoding; Canary's vand128 decodes the 7-bit register indices and shares vand's body (InstrEmit_vand_).

Related Instructions

• vandc — VA & ~VB; useful for clearing bits selected by a mask.
• vor, vxor, vnor — the rest of the bitwise family.
• vsel — bit-wise select using a mask: (VC & VB) | (~VC & VA). The recommended idiom whenever the "false" path is non-zero.
• vcmpequb and other compares — natural mask producers.

IBM Reference

• AIX 7.3 — vand (Vector Logical AND)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Logical Operations