Sylpheed/tools/ppc-manual/vmx/vsel.md

vsel — Vector Conditional Select

Category: VMX (Altivec) · Form: VA · Opcode: 0x1000002a

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vsel	vsel	—	Vector Conditional Select
vsel128	vsel128	—	Vector128 Conditional Select

Syntax

vsel [VD], [VA], [VB], [VC]
vsel128 [VD], [VA], [VB], [VD]

Encoding

vsel — form VA

• Opcode word: 0x1000002a
• Primary opcode (bits 0–5): 4
• Extended opcode: 42
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT	destination vector register
11–15	VRA	source A
16–20	VRB	source B
21–25	VRC	source C / shift
26–31	XO	extended opcode (6 bits)

vsel128 — form VX128

• Opcode word: 0x14000350
• Primary opcode (bits 0–5): 5
• Extended opcode: 848
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4 or 5)
6–10	VD128l	destination low 5 bits
11–15	VA128l	source A low 5 bits
16–20	VB128l	source B low 5 bits
21	VA128H	source A high bit
22	—	reserved
23–25	VC	optional VC / XO sub-field
26	VA128h	source A middle bit
27	—	reserved
28–29	VD128h	destination high 2 bits
30–31	VB128h	source B high 2 bits

Operands

Field	Role	Description
VA	vsel: read; vsel128: read	Source A vector register.
VB	vsel: read; vsel128: read	Source B vector register.
VC	vsel: read	Source C vector register / 3-bit selector.
VD	vsel: write; vsel128: read; vsel128: write	Destination vector register.

Register Effects

vsel

• Reads (always): VA, VB, VC
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

vsel128

• Reads (always): VA, VB, VD
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vsel

• Canary XML: tools/ppc-instructions.xml — search for mnem="vsel"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1362
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:438
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:700

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vsel(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_vsel_(f, i.VXA.VD, i.VXA.VA, i.VXA.VB, i.VXA.VC);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:1354) ──
int InstrEmit_vsel_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb,
                    uint32_t vc) {
  // For each bit:
  // VRTi <- ((VRC)i=0) ? (VRA)i : (VRB)i
  Value* v = f.Select(f.LoadVR(vc), f.LoadVR(va), f.LoadVR(vb));
  f.StoreVR(vd, v);
  return 0;
}

vsel128

• Canary XML: tools/ppc-instructions.xml — search for mnem="vsel128"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1365
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:439
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:744

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vsel128(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_vsel_(f, VX128_VD128, VX128_VA128, VX128_VB128, VX128_VD128);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:1354) ──
int InstrEmit_vsel_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb,
                    uint32_t vc) {
  // For each bit:
  // VRTi <- ((VRC)i=0) ? (VRA)i : (VRB)i
  Value* v = f.Select(f.LoadVR(vc), f.LoadVR(va), f.LoadVR(vb));
  f.StoreVR(vd, v);
  return 0;
}

Special Cases & Edge Conditions

• Per-bit select. VD = (VA & ~VC) | (VB & VC). Evaluated bit-by-bit across the full 128-bit register — not per-lane. Any granularity (byte / half / word) is valid because each bit is independent.
• Classic "bitwise conditional move". The canonical use is: compare produces an all-ones / all-zeros mask in VC, then vsel picks between two data vectors. Because the mask is all-or-nothing per lane, vsel behaves identically to a per-lane conditional move in that common case.
• Mask does not need to be all-ones / all-zeros. Partial masks produce interleaved bits, which is useful for bitfield merges.
• vsel128 read pattern is atypical: the destination VD is also an input. The VMX128 encoding reuses the destination's 7 bits to carry one of the three source operands — Canary's vsel128 passes VD as the select mask VC. Compilers express this as vsel v3, v4, v5, v3 even though v3 is also the destination.
• No flags, no VSCR. No dedicated VMX128 separate-control-register sibling; vsel128 covers the VMX128 case.
• Cheaper than vand + vandc + vor. vsel is a single-cycle primitive on Xenon.

Related Instructions

• vand, vandc, vor, vnor, vxor — the boolean primitives vsel replaces when composed.
• vcmpequb, vcmpequh, vcmpequw, vcmpgtsb and relatives — the usual source of the select mask.
• vperm — byte-level permute; uses an index vector rather than a boolean mask.

IBM Reference

• AIX 7.3 — vsel (Vector Conditional Select)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 3 — Logical Operations