f3c512f2ab
The hand-written parts of the manual still described how the retired xenia-rs interpreter behaved: its snapshots, Rust casts and helpers. Each of those 490 statements is now either restated as what Canary's emitters and x64 backend actually do (at the pinned canary_experimental commit), or dropped where it only made sense for xenia-rs. Checking them turned up claims that were wrong, not just outdated: - VSCR[SAT] is never modelled in Canary (DID_SATURATE is a stub and mfvscr cannot see it); the pages said saturating ops set it stickily. - Canary does not implement lswi/lswx/stswi/stswx, dcbi, mtfsb0/mtfsb1, vmsum*, vmhaddshs, vupkhpx/vupklpx, and most SPRs; pages described them as working. - Traps evaluate TO in Canary; stvebx/stvehx/stvewx store one element, not 16 bytes; mtmsrd writes only EE; fres/frsqrte/vrsqrtefp precision claims and the stfs "rounds under RN / sets FPSCR" claim contradicted the spec. - Reservations are a 64 KiB block bitmap plus a value compare, not per-address tracking. Claims that neither Canary's source nor a public spec settles are marked unverified (NI at boot, vmaddcfp128 operand order, estimate bit-exactness). Generated regions are untouched; re-running the generator changes nothing. Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
129 lines
5.4 KiB
Markdown
129 lines
5.4 KiB
Markdown
# `vcmpequb` — Vector Compare Equal-to Unsigned Byte
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> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VC](../forms/VC.md) · **Opcode:** `0x10000006`
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<!-- GENERATED: BEGIN -->
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## Assembler Mnemonics
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| Mnemonic | XML entry | Flags | Description |
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| --- | --- | --- | --- |
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| `vcmpequb` | `vcmpequb` | — | Vector Compare Equal-to Unsigned Byte |
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| `vcmpequb.` | `vcmpequb` | Rc=1 | Vector Compare Equal-to Unsigned Byte |
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## Syntax
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```asm
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vcmpequb[Rc] [VD], [VA], [VB]
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```
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## Encoding
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### `vcmpequb` — form `VC`
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- **Opcode word:** `0x10000006`
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- **Primary opcode (bits 0–5):** `4`
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- **Extended opcode:** `6`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode (4) |
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| 6–10 | `VRT` | destination vector register |
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| 11–15 | `VRA` | source A |
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| 16–20 | `VRB` | source B |
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| 21 | `Rc` | record-form flag (updates CR6) |
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| 22–31 | `XO` | extended opcode (10 bits) |
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## Operands
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| Field | Role | Description |
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| --- | --- | --- |
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| `VA` | vcmpequb: read | Source A vector register. |
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| `VB` | vcmpequb: read | Source B vector register. |
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| `VD` | vcmpequb: write | Destination vector register. |
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| `CR` | vcmpequb: write (conditional) | Condition-register update. When `Rc=1`, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result. |
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## Register Effects
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### `vcmpequb`
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- **Reads (always):** `VA`, `VB`
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- **Reads (conditional):** _none_
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- **Writes (always):** `VD`
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- **Writes (conditional):** `CR`
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## Status-Register Effects
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- `vcmpequb`: **CR6** ← `[all-true, 0, all-false, 0]` when `Rc=1`.
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## Operation (pseudocode)
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```
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; No hand-written pseudocode for this instruction yet.
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; The authoritative semantics are the Canary emitter snapshot under
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; Implementation References; about half of Canary's emitters open
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; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
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; Every side effect is also enumerated in the Register Effects and
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; Status-Register Effects tables above.
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```
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## C Translation Example
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```c
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/* No hand-written C yet. Translate the Canary emitter snapshot */
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/* under Implementation References; its HIR maps directly: */
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/* f.LoadGPR(n) / f.StoreGPR(n, v) -> r[n] / r[n] = v */
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/* f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n] */
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/* f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters */
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/* wrap them in f.ByteSwap for the big-endian guest value */
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/* f.UpdateCR(n, v) -> CR field n from v's LOW 32 BITS vs 0 */
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/* f.LoadCA / f.StoreCA -> xer.CA; f.StoreSAT -> vscr.SAT */
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/* i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands */
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/* The Register Effects and Status-Register Effects tables above */
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/* enumerate every side effect a faithful translation must emit. */
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```
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## Implementation References
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**`vcmpequb`**
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- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vcmpequb"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
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- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:719`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L719)
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- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:325`](../../../crates/sylpheed-ppc/src/opcode.rs#L325)
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- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:672`](../../../crates/sylpheed-ppc/src/decoder.rs#L672)
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<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>
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```cpp
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int InstrEmit_vcmpequb(PPCHIRBuilder& f, const InstrData& i) {
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return InstrEmit_vcmpxxi_(f, i, vcmpxxi_eq, 1, i.VXR.VD, i.VXR.VA, i.VXR.VB,
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i.VXR.Rc);
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}
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```
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</details>
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<!-- GENERATED: END -->
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## Special Cases & Edge Conditions
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- **Per-byte mask: all-ones / all-zero.** Sixteen byte lanes; `VD[i] = (VA[i] == VB[i]) ? 0xFF : 0x00`. Lane 0 is the most-significant byte after `stvx`.
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- **Sign-agnostic.** Equality compare is identical for signed and unsigned bytes; there is no separate `vcmpeqsb`.
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- **CR6 update when `Rc=1`** (`vcmpequb.`). CR6 = `[lt = all-true, gt = 0, eq = all-false, so = 0]` — packed by Canary's `UpdateCR6`. Standard SIMD-search idiom: `vcmpequb. vMask, vData, vNeedle` then `bc 12,26` to branch when *no* lane matched.
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- **Compose with `vsel`.** Mask drives [`vsel`](vsel.md) to pick per-byte between two source vectors.
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- **Common usage.** `memchr` / `strlen` / character classification — compare against a broadcast byte (often built with [`vspltisb`](vspltisb.md)) and inspect CR6 for early-out.
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- **No `VSCR` interaction, no XER, no traps.**
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- **Aliasing legal.**
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- **No VMX128 sibling.**
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## Related Instructions
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- [`vcmpequh`](vcmpequh.md), [`vcmpequw`](vcmpequw.md) — equality compare at half / word width.
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- [`vcmpgtub`](vcmpgtub.md), [`vcmpgtsb`](vcmpgtsb.md) — `>` at byte width, unsigned / signed.
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- [`vsel`](vsel.md) — primary mask consumer.
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- [`vand`](vand.md), [`vandc`](vandc.md), [`vor`](vor.md), [`vxor`](vxor.md) — mask combinators.
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- [`vspltisb`](vspltisb.md), [`vspltb`](vspltb.md) — broadcast sources for needle patterns.
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## IBM Reference
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- [AIX 7.3 — `vcmpequb` (Vector Compare Equal-to Unsigned Byte)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-vcmpequb-vector-compare-equal-unsigned-byte-instruction)
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- [IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Vector Compares](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf)
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