Sylpheed/tools/ppc-manual/vmx/vmuleuh.md

vmuleuh — Vector Multiply Even Unsigned Half Word

Category: VMX (Altivec) · Form: VX · Opcode: 0x10000248

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vmuleuh	vmuleuh	—	Vector Multiply Even Unsigned Half Word

Syntax

vmuleuh [VD], [VA], [VB]

Encoding

vmuleuh — form VX

• Opcode word: 0x10000248
• Primary opcode (bits 0–5): 4
• Extended opcode: 584
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

Operands

Field	Role	Description
VA	vmuleuh: read	Source A vector register.
VB	vmuleuh: read	Source B vector register.
VD	vmuleuh: write	Destination vector register.

Register Effects

vmuleuh

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vmuleuh

• Canary XML: tools/ppc-instructions.xml — search for mnem="vmuleuh"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1086
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:388
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:600

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vmuleuh(PPCHIRBuilder& f, const InstrData& i) {
  XEINSTRNOTIMPLEMENTED();
  return 1;
}

Special Cases & Edge Conditions

• Even-lane half-word multiply. Only half-word lanes 0, 2, 4, 6 of VA and VB participate (big-endian indexing). Each 16×16 unsigned product widens to an unsigned 32-bit word and is written to the corresponding word lane of VD. The odd half-words are ignored.
• Lane-count reduction. 8 half-word input lanes → 4 word output lanes. Pairing is VD.w[i] = VA.h[2*i] * VB.h[2*i] for i ∈ 0..3.
• No overflow possible. 0xFFFF * 0xFFFF = 0xFFFE0001 — fits in 32 bits. VSCR[SAT] is untouched.
• Pair with vmulouh to multiply every half-word lane. Interleave the two vectors with vmrghw/vmrglw (word-granularity) to rebuild the full element order, or feed both into vmsumuhm variants.
• No Rc, no XER, no FPSCR.
• No VMX128 sibling. Xenon code that needs 16-bit lane multiplies usually goes through vmsumuhm / vmsumuhs.

Related Instructions

• vmulouh — odd-half-word twin.
• vmulesh, vmulosh — signed-half-word even/odd.
• vmuleub, vmuloub — byte-granularity even/odd (→ half-word lanes).
• vmsumuhm, vmsumuhs — fused multiply-sum unsigned-half-word (modulo / saturating).
• vmrghw, vmrglw — interleave results.

IBM Reference

• AIX 7.3 — vmuleuh (Vector Multiply Even Unsigned Half Word)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 4 — Integer Arithmetic