Sylpheed/tools/ppc-manual/vmx/vnmsubfp.md

vnmsubfp — Vector Negative Multiply-Subtract Floating Point

Category: VMX (Altivec) · Form: VA · Opcode: 0x1000002f

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vnmsubfp	vnmsubfp	—	Vector Negative Multiply-Subtract Floating Point
vnmsubfp128	vnmsubfp128	—	Vector128 Negative Multiply-Subtract Floating Point

Syntax

vnmsubfp [VD], [VA], [VC], [VB]
vnmsubfp128 [VD], [VA], [VD], [VB]

Encoding

vnmsubfp — form VA

• Opcode word: 0x1000002f
• Primary opcode (bits 0–5): 4
• Extended opcode: 47
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT	destination vector register
11–15	VRA	source A
16–20	VRB	source B
21–25	VRC	source C / shift
26–31	XO	extended opcode (6 bits)

vnmsubfp128 — form VX128

• Opcode word: 0x14000150
• Primary opcode (bits 0–5): 5
• Extended opcode: 336
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4 or 5)
6–10	VD128l	destination low 5 bits
11–15	VA128l	source A low 5 bits
16–20	VB128l	source B low 5 bits
21	VA128H	source A high bit
22	—	reserved
23–25	VC	optional VC / XO sub-field
26	VA128h	source A middle bit
27	—	reserved
28–29	VD128h	destination high 2 bits
30–31	VB128h	source B high 2 bits

Operands

Field	Role	Description
VA	vnmsubfp: read; vnmsubfp128: read	Source A vector register.
VC	vnmsubfp: read	Source C vector register / 3-bit selector.
VB	vnmsubfp: read; vnmsubfp128: read	Source B vector register.
VD	vnmsubfp: write; vnmsubfp128: read; vnmsubfp128: write	Destination vector register.

Register Effects

vnmsubfp

• Reads (always): VA, VC, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

vnmsubfp128

• Reads (always): VA, VD, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

for each 32-bit float lane i in 0..3:
    VD[i] <- −((VA[i] * VC[i]) − VB[i])

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vnmsubfp

• Canary XML: tools/ppc-instructions.xml — search for mnem="vnmsubfp"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1130
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:394
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:704

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vnmsubfp(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_vnmsubfp_(f, i.VXA.VD, i.VXA.VA, i.VXA.VB, i.VXA.VC);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:1118) ──
int InstrEmit_vnmsubfp_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb,
                        uint32_t vc) {
  // (VD) <- -(((VA) * (VC)) - (VB))
  // NOTE: only one rounding should take place, but that's hard...
  // This really needs VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS but that's AVX.
  // NOTE2: we could make vnmsub a new opcode, and then do it in double
  // precision, rounding after the neg

  Value* v = f.Neg(f.MulSub(f.LoadVR(va), f.LoadVR(vc), f.LoadVR(vb)));
  f.StoreVR(vd, v);
  return 0;
}

vnmsubfp128

• Canary XML: tools/ppc-instructions.xml — search for mnem="vnmsubfp128"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1133
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:395
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:730

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vnmsubfp128(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_vnmsubfp_(f, VX128_VD128, VX128_VA128, VX128_VD128,
                             VX128_VB128);
}

Special Cases & Edge Conditions

• Lane-wise negative multiply-subtract. Each of the four lanes computes VD[i] = −((VA[i] × VC[i]) − VB[i]), i.e. VB[i] − VA[i] × VC[i]. The PowerPC ISA specifies the sequence to behave as if it were fused (single IEEE-754 rounding), and Canary's comment agrees ("only one rounding should take place"). Canary emits Neg(MulSub(…)): fused on FMA3 hosts (vfmsub213ps), a separate multiply and subtract otherwise.
• IEEE-754 binary32 lanes. Follows VSCR[NJ]: denormal inputs/outputs flush to zero when NJ = 1.
• No VSCR[SAT] update. VMX float ops never set saturation.
• No FPSCR effect. Unlike scalar fnmsub[s], vnmsubfp does not touch FPSCR.
• NaN propagation. A NaN in any of VA, VB, or VC yields a NaN in the corresponding lane. Sign-of-NaN is unspecified; in Canary it is whatever the host multiply-subtract produced, with the sign flipped by Neg.
• Big-endian lane indexing. Lane 0 is the MSB-most 4 bytes.
• VMX128 sibling: vnmsubfp128. Identical operation with access to v0..v127.
• No Rc bit on this opcode; it never touches CR.

Related Instructions

• vmaddfp — the positive-rounded fused MAC (VA × VC) + VB.
• vaddfp, vsubfp — the underlying adds/subs.
• vmulfp128 — VMX128-only lane-wise float multiply (no standard Altivec form; there, vmaddfp VD, VA, VC, v0_zero).
• vrefp, vrsqrtefp — Newton iterations that pair with vnmsubfp.
• vmaxfp, vminfp — the other float-arithmetic primitives.

IBM Reference

• AIX 7.3 — vnmsubfp (Vector Negative Multiply-Subtract Floating Point)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 5 — Floating-Point Arithmetic