Sylpheed/tools/ppc-manual/vmx/vaddfp.md

vaddfp — Vector Add Floating Point

Category: VMX (Altivec) · Form: VX · Opcode: 0x1000000a

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vaddfp	vaddfp	—	Vector Add Floating Point
vaddfp128	vaddfp128	—	Vector128 Add Floating Point

Syntax

vaddfp [VD], [VA], [VB]
vaddfp128 [VD], [VA], [VB]

Encoding

vaddfp — form VX

• Opcode word: 0x1000000a
• Primary opcode (bits 0–5): 4
• Extended opcode: 10
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

vaddfp128 — form VX128

• Opcode word: 0x14000010
• Primary opcode (bits 0–5): 5
• Extended opcode: 16
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4 or 5)
6–10	VD128l	destination low 5 bits
11–15	VA128l	source A low 5 bits
16–20	VB128l	source B low 5 bits
21	VA128H	source A high bit
22	—	reserved
23–25	VC	optional VC / XO sub-field
26	VA128h	source A middle bit
27	—	reserved
28–29	VD128h	destination high 2 bits
30–31	VB128h	source B high 2 bits

Operands

Field	Role	Description
VA	vaddfp: read; vaddfp128: read	Source A vector register.
VB	vaddfp: read; vaddfp128: read	Source B vector register.
VD	vaddfp: write; vaddfp128: write	Destination vector register.

Register Effects

vaddfp

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

vaddfp128

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

for each 32-bit float lane i in 0..3:
    VD[i] <- VA[i] + VB[i]

C Translation Example

/* vaddfp VD, VA, VB — lane-wise float add                         */
for (int i = 0; i < 4; ++i) v[insn.VD].f[i] = v[insn.VA].f[i] + v[insn.VB].f[i];

Implementation References

vaddfp

• Canary XML: tools/ppc-instructions.xml — search for mnem="vaddfp"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:341
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:296
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:553

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vaddfp(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_vaddfp_(f, i.VX.VD, i.VX.VA, i.VX.VB);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:335) ──
int InstrEmit_vaddfp_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb) {
  // (VD) <- (VA) + (VB) (4 x fp)
  Value* v = f.VectorAdd(f.LoadVR(va), f.LoadVR(vb), FLOAT32_TYPE);
  f.StoreVR(vd, v);
  return 0;
}

vaddfp128

• Canary XML: tools/ppc-instructions.xml — search for mnem="vaddfp128"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:344
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:297
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:725

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vaddfp128(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_vaddfp_(f, VX128_VD128, VX128_VA128, VX128_VB128);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:335) ──
int InstrEmit_vaddfp_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb) {
  // (VD) <- (VA) + (VB) (4 x fp)
  Value* v = f.VectorAdd(f.LoadVR(va), f.LoadVR(vb), FLOAT32_TYPE);
  f.StoreVR(vd, v);
  return 0;
}

Extended Pseudocode

; Four independent lane-wise IEEE-754 single-precision adds
for i in 0..3:
    VD[i] <- VA[i] + VB[i]                       ; binary32, rounded to nearest

; No FPSCR update (VMX uses VSCR, which only has NJ / SAT — and vaddfp doesn't saturate)

Special Cases & Edge Conditions

• Lane indexing is big-endian. Lane 0 is the most significant 4 bytes of the 128-bit register (the one that appears at the lowest byte offset after a stvx). Canary keeps lanes in PPC order: lvx/stvx byte-swap each 32-bit lane in place (vpshufb with XMMByteSwapMask), so host element i is PPC lane i. When writing C that manipulates individual lanes, index v.f[0] as "the byte 0..3" of the big-endian layout.
• Flush-denormals ("NJ") mode. Altivec is independent of FPSCR — it has its own 2-bit VSCR (NJ for non-Java mode + SAT sticky-saturation). VMX float operations honour VSCR[NJ]: when set, denormal inputs and outputs are flushed to zero. Canary starts every thread with NJ set (vscr_vec low word 0x00010000) and its VMX MXCSR in flush-to-zero + denormals-are-zero mode, while its scalar FPU starts in IEEE mode; mtvscr switches the VMX side off when the guest clears NJ. Whether Xenon boots the same way is unverified.
• No exception, no trap. Altivec floats never raise exceptions. NaN inputs produce NaN outputs; ±∞ − ±∞ yields a NaN; there is no VXISI-style status bit. VSCR[SAT] is not touched by vaddfp (it saturates integer ops, not floats).
• Four independent lanes. Each lane's operation is unaffected by the others. Aliasing between VA, VB, and VD is legal and common (vaddfp v3, v3, v4).
• VMX128 sibling (vaddfp128). Semantics identical; only the register encoding differs. VMX128 uses a 7-bit operand ID per source (and destination) built from two or three non-contiguous bit fields — see categories/vmx128.md. Any bit pattern encodable as a 32-register VX-form is also encodable as a VMX128 form, so compilers picked the more compact form that reached the needed register range.
• On x86-64 hosts. Canary emits vaddps. Because its lvx/stvx swap each 32-bit lane in place rather than reversing all 16 bytes, PPC lane i is host lane i, and vaddps gives the right per-lane result.

Related Instructions

• vsubfp — lane-wise float subtract.
• vmaddfp — lane-wise (VA × VC) + VB (fused multiply-add with single rounding).
• vnmsubfp — −((VA × VC) − VB).
• vmaxfp, vminfp — IEEE-754-aware max/min (NaN propagation).
• vcmpeqfp, vcmpgtfp, vcmpgefp, vcmpbfp — compares producing per-lane all-ones / all-zero masks.
• vrfin, vrfim, vrfip, vrfiz — round to integer (to-nearest / down / up / toward-zero).
• vmulfp128 — the VMX128-only lane-wise multiply (Canary emits a plain Mul); standard Altivec has no vmulfp, and code there uses vmaddfp v, va, vc, v0_zero instead.

IBM Reference

• AIX 7.3 — vaddfp (Vector Add Floating Point)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 5 — Floating-Point Arithmetic