f3c512f2ab
The hand-written parts of the manual still described how the retired xenia-rs interpreter behaved: its snapshots, Rust casts and helpers. Each of those 490 statements is now either restated as what Canary's emitters and x64 backend actually do (at the pinned canary_experimental commit), or dropped where it only made sense for xenia-rs. Checking them turned up claims that were wrong, not just outdated: - VSCR[SAT] is never modelled in Canary (DID_SATURATE is a stub and mfvscr cannot see it); the pages said saturating ops set it stickily. - Canary does not implement lswi/lswx/stswi/stswx, dcbi, mtfsb0/mtfsb1, vmsum*, vmhaddshs, vupkhpx/vupklpx, and most SPRs; pages described them as working. - Traps evaluate TO in Canary; stvebx/stvehx/stvewx store one element, not 16 bytes; mtmsrd writes only EE; fres/frsqrte/vrsqrtefp precision claims and the stfs "rounds under RN / sets FPSCR" claim contradicted the spec. - Reservations are a 64 KiB block bitmap plus a value compare, not per-address tracking. Claims that neither Canary's source nor a public spec settles are marked unverified (NI at boot, vmaddcfp128 operand order, estimate bit-exactness). Generated regions are untouched; re-running the generator changes nothing. Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
187 lines
7.8 KiB
Markdown
187 lines
7.8 KiB
Markdown
# `vsel` — Vector Conditional Select
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> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VA](../forms/VA.md) · **Opcode:** `0x1000002a`
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<!-- GENERATED: BEGIN -->
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## Assembler Mnemonics
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| Mnemonic | XML entry | Flags | Description |
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| --- | --- | --- | --- |
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| `vsel` | `vsel` | — | Vector Conditional Select |
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| `vsel128` | `vsel128` | — | Vector128 Conditional Select |
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## Syntax
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```asm
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vsel [VD], [VA], [VB], [VC]
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vsel128 [VD], [VA], [VB], [VD]
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```
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## Encoding
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### `vsel` — form `VA`
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- **Opcode word:** `0x1000002a`
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- **Primary opcode (bits 0–5):** `4`
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- **Extended opcode:** `42`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode (4) |
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| 6–10 | `VRT` | destination vector register |
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| 11–15 | `VRA` | source A |
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| 16–20 | `VRB` | source B |
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| 21–25 | `VRC` | source C / shift |
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| 26–31 | `XO` | extended opcode (6 bits) |
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### `vsel128` — form `VX128`
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- **Opcode word:** `0x14000350`
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- **Primary opcode (bits 0–5):** `5`
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- **Extended opcode:** `848`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode (4 or 5) |
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| 6–10 | `VD128l` | destination low 5 bits |
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| 11–15 | `VA128l` | source A low 5 bits |
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| 16–20 | `VB128l` | source B low 5 bits |
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| 21 | `VA128H` | source A high bit |
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| 22 | `—` | reserved |
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| 23–25 | `VC` | optional VC / XO sub-field |
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| 26 | `VA128h` | source A middle bit |
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| 27 | `—` | reserved |
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| 28–29 | `VD128h` | destination high 2 bits |
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| 30–31 | `VB128h` | source B high 2 bits |
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## Operands
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| Field | Role | Description |
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| --- | --- | --- |
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| `VA` | vsel: read; vsel128: read | Source A vector register. |
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| `VB` | vsel: read; vsel128: read | Source B vector register. |
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| `VC` | vsel: read | Source C vector register / 3-bit selector. |
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| `VD` | vsel: write; vsel128: read; vsel128: write | Destination vector register. |
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## Register Effects
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### `vsel`
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- **Reads (always):** `VA`, `VB`, `VC`
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- **Reads (conditional):** _none_
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- **Writes (always):** `VD`
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- **Writes (conditional):** _none_
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### `vsel128`
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- **Reads (always):** `VA`, `VB`, `VD`
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- **Reads (conditional):** _none_
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- **Writes (always):** `VD`
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- **Writes (conditional):** _none_
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## Status-Register Effects
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_No condition-register or status-register effects._
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## Operation (pseudocode)
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```
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; No hand-written pseudocode for this instruction yet.
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; The authoritative semantics are the Canary emitter snapshot under
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; Implementation References; about half of Canary's emitters open
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; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
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; Every side effect is also enumerated in the Register Effects and
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; Status-Register Effects tables above.
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```
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## C Translation Example
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```c
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/* No hand-written C yet. Translate the Canary emitter snapshot */
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/* under Implementation References; its HIR maps directly: */
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/* f.LoadGPR(n) / f.StoreGPR(n, v) -> r[n] / r[n] = v */
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/* f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n] */
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/* f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters */
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/* wrap them in f.ByteSwap for the big-endian guest value */
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/* f.UpdateCR(n, v) -> CR field n from v's LOW 32 BITS vs 0 */
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/* f.LoadCA / f.StoreCA -> xer.CA; f.StoreSAT -> vscr.SAT */
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/* i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands */
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/* The Register Effects and Status-Register Effects tables above */
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/* enumerate every side effect a faithful translation must emit. */
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```
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## Implementation References
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**`vsel`**
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- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vsel"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
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- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:1362`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L1362)
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- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:438`](../../../crates/sylpheed-ppc/src/opcode.rs#L438)
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- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:700`](../../../crates/sylpheed-ppc/src/decoder.rs#L700)
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<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>
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```cpp
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int InstrEmit_vsel(PPCHIRBuilder& f, const InstrData& i) {
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return InstrEmit_vsel_(f, i.VXA.VD, i.VXA.VA, i.VXA.VB, i.VXA.VC);
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}
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// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:1354) ──
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int InstrEmit_vsel_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb,
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uint32_t vc) {
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// For each bit:
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// VRTi <- ((VRC)i=0) ? (VRA)i : (VRB)i
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Value* v = f.Select(f.LoadVR(vc), f.LoadVR(va), f.LoadVR(vb));
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f.StoreVR(vd, v);
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return 0;
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}
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```
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</details>
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**`vsel128`**
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- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vsel128"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
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- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:1365`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L1365)
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- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:439`](../../../crates/sylpheed-ppc/src/opcode.rs#L439)
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- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:744`](../../../crates/sylpheed-ppc/src/decoder.rs#L744)
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<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>
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```cpp
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int InstrEmit_vsel128(PPCHIRBuilder& f, const InstrData& i) {
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return InstrEmit_vsel_(f, VX128_VD128, VX128_VA128, VX128_VB128, VX128_VD128);
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}
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// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:1354) ──
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int InstrEmit_vsel_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb,
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uint32_t vc) {
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// For each bit:
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// VRTi <- ((VRC)i=0) ? (VRA)i : (VRB)i
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Value* v = f.Select(f.LoadVR(vc), f.LoadVR(va), f.LoadVR(vb));
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f.StoreVR(vd, v);
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return 0;
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}
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```
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</details>
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<!-- GENERATED: END -->
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## Special Cases & Edge Conditions
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- **Per-bit select.** `VD = (VA & ~VC) | (VB & VC)`. Evaluated bit-by-bit across the full 128-bit register — not per-lane. Any granularity (byte / half / word) is valid because each bit is independent.
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- **Classic "bitwise conditional move".** The canonical use is: compare produces an all-ones / all-zeros mask in `VC`, then `vsel` picks between two data vectors. Because the mask is all-or-nothing per lane, `vsel` behaves identically to a per-lane conditional move in that common case.
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- **Mask does not need to be all-ones / all-zeros.** Partial masks produce interleaved bits, which is useful for bitfield merges.
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- **`vsel128` read pattern is atypical:** the destination `VD` is **also an input**. The VMX128 encoding reuses the destination's 7 bits to carry one of the three source operands — Canary's `vsel128` passes `VD` as the select mask `VC`. Compilers express this as `vsel v3, v4, v5, v3` even though `v3` is also the destination.
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- **No flags, no VSCR.** No dedicated VMX128 separate-control-register sibling; `vsel128` covers the VMX128 case.
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- **Cheaper than `vand` + `vandc` + `vor`.** `vsel` is a single-cycle primitive on Xenon.
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## Related Instructions
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- [`vand`](vand.md), [`vandc`](vandc.md), [`vor`](vor.md), [`vnor`](vnor.md), [`vxor`](vxor.md) — the boolean primitives `vsel` replaces when composed.
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- [`vcmpequb`](vcmpequb.md), [`vcmpequh`](vcmpequh.md), [`vcmpequw`](vcmpequw.md), [`vcmpgtsb`](vcmpgtsb.md) and relatives — the usual source of the select mask.
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- [`vperm`](vperm.md) — byte-level permute; uses an index vector rather than a boolean mask.
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## IBM Reference
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- [AIX 7.3 — `vsel` (Vector Conditional Select)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-vsel-vector-conditional-select-instruction)
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- [IBM AltiVec Technology Programmer's Interface Manual, Chapter 3 — Logical Operations](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf)
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