9bfe96e44d
- Category pages linked each family as `<slug>.md`, relative to categories/, where no family page lives. They now link `../<category>/<slug>.md`. - Form pages linked a member into its *own* category directory, so every VMX128 sibling (`vsldoi128`) pointed at vmx128/ although its family page is under vmx/. They now link into the family's directory. - Hand-written "Related" and sibling mentions linked other categories' pages as if they were in the same directory. 109 are retargeted through the page index; 29 that pointed a family page at itself (`vrefp128` on vrefp.md) and 6 naming instructions the manual has no page for are plain text now. Regenerated at the existing Canary pin (f21ebd49e): upstream has moved on, and re-pinning belongs in its own change. The generator reports 0 family pages changed and is idempotent; the only dead links left are TEMPLATE.md's placeholders. Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
182 lines
6.7 KiB
Markdown
182 lines
6.7 KiB
Markdown
# `vsrw` — Vector Shift Right Word
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> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VX](../forms/VX.md) · **Opcode:** `0x10000284`
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<!-- GENERATED: BEGIN -->
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## Assembler Mnemonics
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| Mnemonic | XML entry | Flags | Description |
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| --- | --- | --- | --- |
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| `vsrw` | `vsrw` | — | Vector Shift Right Word |
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| `vsrw128` | `vsrw128` | — | Vector128 Shift Right Word |
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## Syntax
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```asm
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vsrw [VD], [VA], [VB]
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vsrw128 [VD], [VA], [VB]
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```
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## Encoding
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### `vsrw` — form `VX`
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- **Opcode word:** `0x10000284`
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- **Primary opcode (bits 0–5):** `4`
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- **Extended opcode:** `644`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode (4) |
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| 6–10 | `VRT/VD` | destination vector register |
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| 11–15 | `VRA/VA` | source A vector register |
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| 16–20 | `VRB/VB` | source B vector register |
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| 21–31 | `XO` | extended opcode (11 bits) |
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### `vsrw128` — form `VX128`
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- **Opcode word:** `0x180001d0`
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- **Primary opcode (bits 0–5):** `6`
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- **Extended opcode:** `464`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode (4 or 5) |
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| 6–10 | `VD128l` | destination low 5 bits |
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| 11–15 | `VA128l` | source A low 5 bits |
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| 16–20 | `VB128l` | source B low 5 bits |
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| 21 | `VA128H` | source A high bit |
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| 22 | `—` | reserved |
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| 23–25 | `VC` | optional VC / XO sub-field |
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| 26 | `VA128h` | source A middle bit |
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| 27 | `—` | reserved |
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| 28–29 | `VD128h` | destination high 2 bits |
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| 30–31 | `VB128h` | source B high 2 bits |
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## Operands
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| Field | Role | Description |
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| --- | --- | --- |
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| `VA` | vsrw: read; vsrw128: read | Source A vector register. |
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| `VB` | vsrw: read; vsrw128: read | Source B vector register. |
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| `VD` | vsrw: write; vsrw128: write | Destination vector register. |
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## Register Effects
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### `vsrw`
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- **Reads (always):** `VA`, `VB`
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- **Reads (conditional):** _none_
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- **Writes (always):** `VD`
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- **Writes (conditional):** _none_
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### `vsrw128`
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- **Reads (always):** `VA`, `VB`
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- **Reads (conditional):** _none_
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- **Writes (always):** `VD`
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- **Writes (conditional):** _none_
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## Status-Register Effects
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_No condition-register or status-register effects._
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## Operation (pseudocode)
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```
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; No hand-written pseudocode for this instruction yet.
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; The authoritative semantics are the Canary emitter snapshot under
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; Implementation References; about half of Canary's emitters open
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; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
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; Every side effect is also enumerated in the Register Effects and
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; Status-Register Effects tables above.
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```
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## C Translation Example
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```c
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/* No hand-written C yet. Translate the Canary emitter snapshot */
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/* under Implementation References; its HIR maps directly: */
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/* f.LoadGPR(n) / f.StoreGPR(n, v) -> r[n] / r[n] = v */
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/* f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n] */
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/* f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters */
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/* wrap them in f.ByteSwap for the big-endian guest value */
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/* f.UpdateCR(n, v) -> CR field n from v's LOW 32 BITS vs 0 */
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/* f.LoadCA / f.StoreCA -> xer.CA; f.StoreSAT -> vscr.SAT */
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/* i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands */
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/* The Register Effects and Status-Register Effects tables above */
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/* enumerate every side effect a faithful translation must emit. */
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```
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## Implementation References
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**`vsrw`**
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- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vsrw"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
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- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:1650`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L1650)
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- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:466`](../../../crates/sylpheed-ppc/src/opcode.rs#L466)
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- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:606`](../../../crates/sylpheed-ppc/src/decoder.rs#L606)
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<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>
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```cpp
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int InstrEmit_vsrw(PPCHIRBuilder& f, const InstrData& i) {
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return InstrEmit_vsrw_(f, i.VX.VD, i.VX.VA, i.VX.VB);
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}
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// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:1644) ──
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int InstrEmit_vsrw_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb) {
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// (VD) <- (VA) >> (VB) by words
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Value* v = f.VectorShr(f.LoadVR(va), f.LoadVR(vb), INT32_TYPE);
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f.StoreVR(vd, v);
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return 0;
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}
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```
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</details>
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**`vsrw128`**
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- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vsrw128"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
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- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:1653`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L1653)
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- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:467`](../../../crates/sylpheed-ppc/src/opcode.rs#L467)
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- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:810`](../../../crates/sylpheed-ppc/src/decoder.rs#L810)
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<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>
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```cpp
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int InstrEmit_vsrw128(PPCHIRBuilder& f, const InstrData& i) {
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return InstrEmit_vsrw_(f, VX128_VD128, VX128_VA128, VX128_VB128);
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}
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// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:1644) ──
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int InstrEmit_vsrw_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb) {
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// (VD) <- (VA) >> (VB) by words
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Value* v = f.VectorShr(f.LoadVR(va), f.LoadVR(vb), INT32_TYPE);
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f.StoreVR(vd, v);
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return 0;
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}
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```
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</details>
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<!-- GENERATED: END -->
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## Special Cases & Edge Conditions
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- **Per-lane logical right-shift of words.** `VD.w[i] = VA.w[i] >> (VB.w[i] & 0x1F)` — zero-fill. Low 5 bits of each shift-count word honoured.
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- **Per-lane shift counts.** Splat via [`vspltw`](vspltw.md) / [`vspltisw`](vspltisw.md) for uniform shifts.
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- **Zero-fill.** Use [`vsraw`](vsraw.md) for sign-preserving right shift.
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- **Big-endian word lanes.**
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- **No flags, no VSCR.**
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- **VMX128 sibling `vsrw128`.**
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## Related Instructions
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- [`vsraw`](vsraw.md) — arithmetic-right word.
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- [`vslw`](vslw.md) — logical-left word.
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- [`vrlw`](vrlw.md) — word rotate.
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- [`vsrb`](vsrb.md), [`vsrh`](vsrh.md) — byte / half-word logical-right.
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## IBM Reference
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- [AIX 7.3 — `vsrw` (Vector Shift Right Integer Word)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-vsrw-vector-shift-right-integer-word-instruction)
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- [IBM AltiVec Technology Programmer's Interface Manual, Chapter 4 — Integer Shift / Rotate](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf)
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