Sylpheed/tools/ppc-manual/vmx128/vcfpuxws128.md

vcfpuxws128 — Vector128 Convert From Floating-Point to Unsigned Fixed-Point Word Saturate

Category: VMX128 · Form: VX128_3 · Opcode: 0x18000270

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vcfpuxws128	vcfpuxws128	—	Vector128 Convert From Floating-Point to Unsigned Fixed-Point Word Saturate

Syntax

vcfpuxws128 [VD], [VB], [UIMM]

Encoding

vcfpuxws128 — form VX128_3

• Opcode word: 0x18000270
• Primary opcode (bits 0–5): 6
• Extended opcode: 624
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (6)
6–10	VD128l	destination low 5 bits
11–15	IMM	5-bit immediate
16–20	VB128l	source B low 5 bits
21–27	XO	extended opcode
28–29	VD128h	destination high 2 bits
30–31	VB128h	source B high 2 bits

Operands

Field	Role	Description
VB	vcfpuxws128: read	Source B vector register.
UIMM	vcfpuxws128: read	16-bit unsigned immediate. Zero-extended.
VD	vcfpuxws128: write	Destination vector register.
VSCR	vcfpuxws128: write	Vector Status and Control Register (NJ/SAT bits).

Register Effects

vcfpuxws128

• Reads (always): VB, UIMM
• Reads (conditional): none
• Writes (always): VD, VSCR
• Writes (conditional): none

Status-Register Effects

• vcfpuxws128: VSCR[SAT] may be stickied on saturating vector operations.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vcfpuxws128

• Canary XML: tools/ppc-instructions.xml — search for mnem="vcfpuxws128"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:557
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:318
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:772

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vcfpuxws128(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_vctuxs_(f, VX128_3_VD128, VX128_3_VB128, VX128_3_IMM);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:543) ──
int InstrEmit_vctuxs_(PPCHIRBuilder& f, uint32_t vd, uint32_t vb,
                      uint32_t uimm) {
  // (VD) <- int_sat(VB as unsigned * 2^uimm)
  float fuimm = static_cast<float>(std::exp2(uimm));
  Value* v =
      f.Mul(f.LoadVR(vb), f.Splat(f.LoadConstantFloat32(fuimm), VEC128_TYPE));
  v = f.VectorConvertF2I(v, ARITHMETIC_UNSIGNED);
  f.StoreSAT(f.DidSaturate(v));
  f.StoreVR(vd, v);
  return 0;
}

Special Cases & Edge Conditions

• Float → unsigned fixed-point (uint32) with explicit scale. Each lane computes VD.w[i] = sat_uint32(VB[i] * 2^UIMM), truncating toward zero and clamping to [0, 2^32−1]. UIMM is a 5-bit unsigned bias (range 0..31).
• Negative floats clamp to 0 and sticky-set VSCR[SAT].
• NaN inputs → 0. Canary shares vctuxs's body, whose vmaxps against zero turns NaN into 0; it never records VSCR[SAT].
• VSCR[NJ] honoured for denormal inputs.
• VMX128 register-fusion applies to VD and VB (7-bit IDs).
• No IBM AIX entry — Xenon-only.
• No Rc, no XER / FPSCR.

Related Instructions

• vctuxs — the standard Altivec equivalent (uint32 clamp with scale).
• vcfpsxws128 — signed variant.
• vcuxwfp128 — the inverse (uint → float with scale).
• vrfiz — plain truncate-to-integer-float without scale.

IBM Reference

• No IBM AIX entry — this instruction is exclusive to the Xbox 360's VMX128 extension.
• Xbox 360 XDK, Altivec-128 (VMX128) extensions (Microsoft internal documentation); cross-referenced with IBM AltiVec Technology Programmer's Interface Manual §vctuxs.