Sylpheed/tools/ppc-manual/vmx128/vcuxwfp128.md

vcuxwfp128 — Vector128 Convert From Unsigned Fixed-Point Word to Floating-Point

Category: VMX128 · Form: VX128_3 · Opcode: 0x180002f0

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vcuxwfp128	vcuxwfp128	—	Vector128 Convert From Unsigned Fixed-Point Word to Floating-Point

Syntax

vcuxwfp128 [VD], [VB], [UIMM]

Encoding

vcuxwfp128 — form VX128_3

• Opcode word: 0x180002f0
• Primary opcode (bits 0–5): 6
• Extended opcode: 752
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (6)
6–10	VD128l	destination low 5 bits
11–15	IMM	5-bit immediate
16–20	VB128l	source B low 5 bits
21–27	XO	extended opcode
28–29	VD128h	destination high 2 bits
30–31	VB128h	source B high 2 bits

Operands

Field	Role	Description
VB	vcuxwfp128: read	Source B vector register.
UIMM	vcuxwfp128: read	16-bit unsigned immediate. Zero-extended.
VD	vcuxwfp128: write	Destination vector register.

Register Effects

vcuxwfp128

• Reads (always): VB, UIMM
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vcuxwfp128

• Canary XML: tools/ppc-instructions.xml — search for mnem="vcuxwfp128"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:521
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:342
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:774

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vcuxwfp128(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_vcfux_(f, VX128_3_VD128, VX128_3_VB128, VX128_3_IMM);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:507) ──
int InstrEmit_vcfux_(PPCHIRBuilder& f, uint32_t vd, uint32_t vb,
                     uint32_t uimm) {
  // (VD) <- float(VB as unsigned) / 2^uimm
  Value* v = f.VectorConvertI2F(f.LoadVR(vb), ARITHMETIC_UNSIGNED);
  if (uimm) {
    float fuimm = std::ldexp(1.0f, -int(uimm));
    v = f.Mul(v, f.Splat(f.LoadConstantFloat32(fuimm), VEC128_TYPE));
  }
  f.StoreVR(vd, v);
  return 0;
}

Special Cases & Edge Conditions

• Unsigned fixed-point (uint32) → float with explicit scale. Each lane computes VD[i] = (float)VB.w[i] * 2^-UIMM. Treats the 32-bit input as unsigned, so values ≥ 0x80000000 produce positive floats (unlike vcsxwfp128 which would produce negatives).
• IEEE-754 binary32 output, round-to-nearest. Precision loss above 2^24.
• No VSCR[SAT] effect.
• VSCR[NJ] does not affect the uint → float path.
• VMX128 register-fusion applies.
• No IBM AIX entry — Xenon-only. Closest standard is vcfux.
• No Rc, no XER / FPSCR.

Related Instructions

• vcfux — the standard Altivec uint32 → float with scale.
• vcsxwfp128 — signed-int variant.
• vcfpuxws128, vcfpsxws128 — the inverse (float → int with scale).

IBM Reference

• No IBM AIX entry — Xbox 360 VMX128 extension only.
• Xbox 360 XDK, Altivec-128 (VMX128) extensions; cross-referenced with IBM AltiVec Technology Programmer's Interface Manual §vcfux.