Sylpheed/tools/ppc-manual/alu/addicx.md

addic. — Add Immediate Carrying and Record

Category: Integer ALU · Form: D · Opcode: 0x34000000

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
addic.	addic.	—	Add Immediate Carrying and Record

Syntax

addic. [RD], [RA], [SIMM]

Encoding

addic. — form D

• Opcode word: 0x34000000
• Primary opcode (bits 0–5): 13
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT	destination GPR (or RS when storing)
11–15	RA	source GPR (0 ⇒ literal 0 for RA0 forms)
16–31	D/SI/UI	16-bit signed or unsigned immediate

Operands

Field	Role	Description
RA	addic.: read	Source GPR (r0–r31).
SIMM	addic.: read	16-bit signed immediate. Sign-extended to 64 bits before use.
RD	addic.: write	Destination GPR.
CA	addic.: write	XER[CA] carry bit. Read by add-with-carry/subtract-with-borrow instructions, written by carrying instructions.
CR	addic.: write	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

addic.

• Reads (always): RA, SIMM
• Reads (conditional): none
• Writes (always): RD, CA, CR
• Writes (conditional): none

Status-Register Effects

• addic.: CR0 ← signed-compare(result, 0) with SO ← XER[SO] (always).; XER[CA] ← carry-out of the add / borrow-in of the subtract (always).

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

addic.

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="addic."
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_alu.cc:127
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:8
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:337
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:145-154

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::addicx => {
            // PPCBUG-003: same fix as addic plus CR0 i32 view.
            let ra32 = ctx.gpr[instr.ra()] as u32;
            let imm32 = instr.simm16() as i32 as u32;
            let result32 = ra32.wrapping_add(imm32);
            ctx.xer_ca = if result32 < ra32 { 1 } else { 0 };
            ctx.gpr[instr.rd()] = result32 as u64;
            ctx.update_cr_signed(0, result32 as i32 as i64);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Rc bit is implicit, not encoded. addic. has its own primary opcode (13) distinct from addic's (12); there is no Rc field to set. The two forms are sibling D-form instructions, not flag variants of one encoding.
• CR0 update is unconditional. Unlike XO-form Rc=1 instructions, addic. always updates CR0 from the result; the . is part of the mnemonic itself.
• Common idiom: addic. rN, rN, -1 — decrements rN and sets CR0[EQ] when it reaches zero, in a single instruction. Frequently used as a loop counter (often paired with bne+ loop).
• XER[CA] written same as addic. The carry-out from the unsigned 64-bit add is recorded; the . only adds the CR update on top.
• 64-bit CR update on Xenon, 32-bit in xenia-rs. interpreter.rs:65 computes result as i32 as i64; spec demands a full 64-bit compare-to-zero. The truncation is a documented xenia-rs quirk shared with the rest of the carrying-add family.
• SIMM is sign-extended to 64 bits before the add — addic. r3, r4, -1 adds ~0 and never sets CR0[EQ] unless r4 == 1.

Related Instructions

• addic — same op without the CR0 update.
• addi, addis — immediate adds without XER[CA].
• addcx — XO-form register equivalent.
• subfic — RT ← SIMM − RA with XER[CA] (no record form exists).
• cmpi — explicit immediate compare when the carry side-effect would be unwanted.

IBM Reference

• AIX 7.3 — addic. (Add Immediate Carrying and Record)