Sylpheed/tools/ppc-manual/alu/andcx.md

andcx — AND with Complement

Category: Integer ALU · Form: X · Opcode: 0x7c000078

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
andc	andcx	—	AND with Complement
andc.	andcx	Rc=1	AND with Complement

Syntax

andc[Rc] [RA], [RS], [RB]

Encoding

andcx — form X

• Opcode word: 0x7c000078
• Primary opcode (bits 0–5): 31
• Extended opcode: 60
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RS	andcx: read	Source GPR (alias for RD in some stores).
RB	andcx: read	Source GPR.
RA	andcx: write	Source GPR (r0–r31).
CR	andcx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

andcx

• Reads (always): RS, RB
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): CR

Status-Register Effects

• andcx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

RA <- (RS) & ~(RB)

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

andcx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="andcx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_alu.cc:647
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:9
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:768
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:534-541

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::andcx => {
            // PPCBUG-033: !rb on u64 flips upper 32 bits — active poisoning.
            let rs32 = ctx.gpr[instr.rs()] as u32;
            let rb32 = ctx.gpr[instr.rb()] as u32;
            ctx.gpr[instr.ra()] = (rs32 & !rb32) as u64;
            if instr.rc_bit() { ctx.update_cr_signed(0, ctx.gpr[instr.ra()] as u32 as i32 as i64); }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• andc RA, RS, RB computes RS AND (NOT RB). The complement is applied to RB, not RS. Useful for clearing a bitmask: andc r3, r3, r4 clears in r3 every bit set in r4.
• Common idiom: andc r3, r3, r3 zeroes r3 (every bit ANDed with its own complement). Cheaper-looking than xor r3, r3, r3 on some pipelines but functionally identical; the assembler often prefers the xor idiom.
• Operand convention is the X-form one (RA is the destination, RS and RB are sources). Same gotcha as andx.
• No OE/XER side effects. Only CR0 is updated when Rc=1.
• 64-bit operation on Xenon; the AND is computed across all 64 bits of RS and ~RB. Xenia-rs uses Rust's bitwise ! on u64, which is the correct full-width complement.
• 64-bit CR update on Xenon, 32-bit in xenia-rs. interpreter.rs:352 — same truncation pattern.

Related Instructions

• andx — plain AND (no complement).
• nandx — NAND (~(RS & RB)).
• orcx — OR with complement; sister c form.
• eqvx — ~(RS ^ RB) (NXOR / equivalence).
• norx — NOR.

IBM Reference

• AIX 7.3 — andc (AND with Complement)