Sylpheed/tools/ppc-manual/alu/mulhdux.md

mulhdux — Multiply High Doubleword Unsigned

Category: Integer ALU · Form: XO · Opcode: 0x7c000012

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
mulhdu	mulhdux	—	Multiply High Doubleword Unsigned
mulhdu.	mulhdux	Rc=1	Multiply High Doubleword Unsigned

Syntax

mulhdu[Rc] [RD], [RA], [RB]

Encoding

mulhdux — form XO

• Opcode word: 0x7c000012
• Primary opcode (bits 0–5): 31
• Extended opcode: 9
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (31)
6–10	RT	destination GPR
11–15	RA	source A
16–20	RB	source B
21	OE	overflow-enable flag
22–30	XO	extended opcode (9 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RA	mulhdux: read	Source GPR (r0–r31).
RB	mulhdux: read	Source GPR.
RD	mulhdux: write	Destination GPR.
CR	mulhdux: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

mulhdux

• Reads (always): RA, RB
• Reads (conditional): none
• Writes (always): RD
• Writes (conditional): CR

Status-Register Effects

• mulhdux: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

RT <- ((RA) * (RB))[0:63]               ; high 64 of unsigned 64×64

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

mulhdux

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="mulhdux"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_alu.cc:311
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:57
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:860
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:454-462

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::mulhdux => {
            let ra = ctx.gpr[instr.ra()] as u128;
            let rb = ctx.gpr[instr.rb()] as u128;
            ctx.gpr[instr.rd()] = (ra.wrapping_mul(rb) >> 64) as u64;
            if instr.rc_bit() {
                ctx.update_cr_signed(0, ctx.gpr[instr.rd()] as i64);
            }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Returns the high 64 bits of an unsigned 64×64 product. Operands are zero-extended (treated as unsigned) before multiplication. Pair with mulldx for the low 64 bits to form a full 128-bit unsigned product.
• No OE bit. No overflow signal — the high half is a defined function of the inputs even when the product fills 128 bits.
• Xenia uses native u128. interpreter.rs:284 widens both operands then shifts. Note as u128 zero-extends, in contrast to mulhdx's as i64 as i128 which sign-extends — this is the entire semantic difference.
• Rc=1 CR0 update is correctly 64-bit. Uses as i64 directly. Because the high half is unsigned, treating it as signed for CR0 means very large unsigned values appear LT — keep this in mind when interpreting the CR0 bits after mulhdu..
• Used in reciprocal-multiply division strategies. Compilers may strength-reduce divide-by-constant into mulhdu plus a shift; appears in optimised disassembly.
• Slow. Same multi-cycle cost as the signed variant.

Related Instructions

• mulldx — low 64 bits of the same unsigned product.
• mulhdx — signed high half.
• mulhwux — 32-bit unsigned high half.
• divdux — 64-bit unsigned divide; sometimes replaced by reciprocal mulhdu.

IBM Reference

• AIX 7.3 — mulhdu (Multiply High Doubleword Unsigned)