Sylpheed/tools/ppc-manual/alu/xorx.md

xorx — XOR

Category: Integer ALU · Form: X · Opcode: 0x7c000278

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
xor	xorx	—	XOR
xor.	xorx	Rc=1	XOR

Syntax

xor[Rc] [RA], [RS], [RB]

Encoding

xorx — form X

• Opcode word: 0x7c000278
• Primary opcode (bits 0–5): 31
• Extended opcode: 316
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RS	xorx: read	Source GPR (alias for RD in some stores).
RB	xorx: read	Source GPR.
RA	xorx: write	Source GPR (r0–r31).
CR	xorx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

xorx

• Reads (always): RS, RB
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): CR

Status-Register Effects

• xorx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

RA <- (RS) ^ (RB)

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

xorx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="xorx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_alu.cc:829
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:132
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:798
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:556-561

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::xorx => {
            // PPCBUG-032+020: 32-bit ABI CR0 view.
            ctx.gpr[instr.ra()] = ctx.gpr[instr.rs()] ^ ctx.gpr[instr.rb()];
            if instr.rc_bit() { ctx.update_cr_signed(0, ctx.gpr[instr.ra()] as u32 as i32 as i64); }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• RA ← RS XOR RB. Bit-wise XOR.
• Idiom: xor RA, RS, RS zeroes RA — the canonical "clear register" instruction. Cheaper than li RA, 0 because no immediate-extraction stage is involved.
• Operand convention is X-form (RA destination, RS/RB sources).
• 64-bit operation on Xenon.
• No OE or XER side effects. Only Rc=1 updates CR0.
• 64-bit CR update on Xenon, 32-bit in xenia-rs. interpreter.rs:367 truncates with as i32 as i64. For xor. whose result has differing high/low halves, spec and xenia diverge; xor. RA, RS, RS gives EQ either way.
• Useful as bitmask toggle. xor r3, r3, r4 flips in r3 every bit set in r4.
• No XER[CA].

Related Instructions

• xori, xoris — D-form immediate variants.
• eqvx — NXOR (~(RS ^ RB)).
• andx, orx, norx, nandx — sister logicals.

IBM Reference

• AIX 7.3 — xor (XOR)