Sylpheed/tools/ppc-manual/control/mfcr.md

mfcr — Move from Condition Register

Category: Control / CR / SPR · Form: X · Opcode: 0x7c000026

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
mfcr	mfcr	—	Move from Condition Register

Syntax

mfcr [RD]

Encoding

mfcr — form X

• Opcode word: 0x7c000026
• Primary opcode (bits 0–5): 31
• Extended opcode: 19
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
CR	mfcr: read	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.
RD	mfcr: write	Destination GPR.

Register Effects

mfcr

• Reads (always): CR
• Reads (conditional): none
• Writes (always): RD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

RT <- 0x00000000 || CR

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

mfcr

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="mfcr"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_control.cc:625
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:53
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:753
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:1627-1630

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::mfcr => {
            ctx.gpr[instr.rd()] = ctx.cr() as u64;
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Operation. Packs all 32 CR bits into the low half of RD; the upper 32 bits of RD are zeroed. CR field 0 ends up in bits 32..35 of RD (i.e. bits 0..3 of the 32-bit packed value), CR field 7 in bits 60..63 (bits 28..31).
• No CR side effect. mfcr is a read; CR is unmodified. The XL-form's nominal Rc bit is unused on this opcode.
• Saving CR across calls. The Xbox 360 / SysV ABI requires non-volatile CR fields (CR2..CR4) to be preserved across calls. Standard prologue: mfcr r12; stw r12, 8(r1). Epilogue restores via mtcrf.
• Bit ordering. PowerPC numbers bits big-endian (bit 0 = MSB). The encoding into the GPR follows the same convention: CR0.LT lands in bit 32 of the doubleword (the MSB of the low word). C-side translations should mask with 0xFFFFFFFFu before consuming.
• mfocrf variant. PowerISA defines mfocrf (one CR field), encoded as mfcr with the high bit of FXM set. xenia-rs decodes both as the same opcode and ignores the FXM hint, returning the entire CR. This is benign — the spec says implementations may treat mfocrf as mfcr.
• Not synchronising. Reorderable.
• xenia exact match. xenia-rs packs its eight CrField structs into a u64 via ctx.cr(), mirroring spec semantics.

Related Instructions

• mtcrf — inverse: write selected CR fields from a GPR.
• mcrf, mcrxr, mcrfs — narrower CR-field moves.
• mfspr, mtspr — generic SPR moves; CR is not an SPR (it has its own opcode).

mfcr has no simplified mnemonics. mfocrf RT, FXM is a related encoding handled by the same xenia-rs slot.

IBM Reference

• AIX 7.3 — mfcr (Move from Condition Register)