Sylpheed/tools/ppc-manual/memory/lhz.md

lhz — Load Half Word and Zero

Category: Memory · Form: D · Opcode: 0xa0000000

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
lhz	lhz	—	Load Half Word and Zero
lhzu	lhzu	—	Load Half Word and Zero with Update
lhzux	lhzux	—	Load Half Word and Zero with Update Indexed
lhzx	lhzx	—	Load Half Word and Zero Indexed

Syntax

lhz [RD], [d]([RA0])
lhzu [RD], [d]([RA])
lhzux [RD], [RA], [RB]
lhzx [RD], [RA0], [RB]

Encoding

lhz — form D

• Opcode word: 0xa0000000
• Primary opcode (bits 0–5): 40
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT	destination GPR (or RS when storing)
11–15	RA	source GPR (0 ⇒ literal 0 for RA0 forms)
16–31	D/SI/UI	16-bit signed or unsigned immediate

lhzu — form D

• Opcode word: 0xa4000000
• Primary opcode (bits 0–5): 41
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT	destination GPR (or RS when storing)
11–15	RA	source GPR (0 ⇒ literal 0 for RA0 forms)
16–31	D/SI/UI	16-bit signed or unsigned immediate

lhzux — form X

• Opcode word: 0x7c00026e
• Primary opcode (bits 0–5): 31
• Extended opcode: 311
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

lhzx — form X

• Opcode word: 0x7c00022e
• Primary opcode (bits 0–5): 31
• Extended opcode: 279
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RA0	lhz: read; lhzx: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.
d	lhz: read; lhzu: read	16-bit signed displacement (d) added to the base address register.
RD	lhz: write; lhzu: write; lhzux: write; lhzx: write	Destination GPR.
RA	lhzu: read; lhzu: write; lhzux: read; lhzux: write	Source GPR (r0–r31).
RB	lhzux: read; lhzx: read	Source GPR.

Register Effects

lhz

• Reads (always): RA0, d
• Reads (conditional): none
• Writes (always): RD
• Writes (conditional): none

lhzu

• Reads (always): RA, d
• Reads (conditional): none
• Writes (always): RD, RA
• Writes (conditional): none

lhzux

• Reads (always): RA, RB
• Reads (conditional): none
• Writes (always): RD, RA
• Writes (conditional): none

lhzx

• Reads (always): RA0, RB
• Reads (conditional): none
• Writes (always): RD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

EA <- (RA|0) + EXTS(d)
RT <- ZEXT16_to_64(MEM(EA, 2))

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

lhz

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="lhz"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_memory.cc:186
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:40
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:363
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:1048-1053

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::lhz => {
            let ea = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
            let ea = ea.wrapping_add(instr.d() as i64 as u64) as u32;
            ctx.gpr[instr.rd()] = mem.read_u16(ea) as u64;
            ctx.pc += 4;
        }

lhzu

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="lhzu"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_memory.cc:207
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:40
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:364
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:1054-1059

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::lhzu => {
            let ea = ctx.gpr[instr.ra()].wrapping_add(instr.d() as i64 as u64) as u32;
            ctx.gpr[instr.rd()] = mem.read_u16(ea) as u64;
            ctx.gpr[instr.ra()] = ea as u64;
            ctx.pc += 4;
        }

lhzux

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="lhzux"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_memory.cc:220
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:40
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:797
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:1078-1083

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::lhzux => {
            let ea = ctx.gpr[instr.ra()].wrapping_add(ctx.gpr[instr.rb()]) as u32;
            ctx.gpr[instr.rd()] = mem.read_u16(ea) as u64;
            ctx.gpr[instr.ra()] = ea as u64;
            ctx.pc += 4;
        }

lhzx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="lhzx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_memory.cc:231
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:40
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:795
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:1060-1065

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::lhzx => {
            let ea = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
            let ea = ea.wrapping_add(ctx.gpr[instr.rb()]) as u32;
            ctx.gpr[instr.rd()] = mem.read_u16(ea) as u64;
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Big-endian read, zero-extension. Reads 2 bytes big-endian, treats them as an unsigned 16-bit integer, zero-extends to 64 bits. The high 48 bits of RT become zero. Compare with lha, which sign-extends.
• RA0 (non-update forms). RA = 0 in lhz / lhzx selects literal zero for absolute-address access. Update forms lhzu / lhzux invoke RA = 0 and RA = RT as invalid forms.
• Update-form ordering. Xenia computes EA, performs the load, then writes RA ← EA. If RA == RT (an invalid form per IBM), the load result is overwritten by EA immediately.
• No alignment requirement. Xenon executes unaligned half-word loads without faulting. MEM(EA, 2) reads the two consecutive bytes at EA.
• Common as Unicode codepoint loader. Xbox 360 system strings are UTF-16; lhz is the canonical load for a single 16-bit codepoint.
• Use lhz rather than lbz × 2 + shift. One fused instruction is faster and lets the load-store unit handle alignment.
• Indexed variant operand order. lhzx RT, RA, RB — RA is the base (with RA0 semantics), RB is the offset.

Related Instructions

• lha, lhau, lhax, lhaux — sign-extending counterparts.
• lbz, lwz, ld — narrower / wider zero-extending loads.
• lhbrx — byte-reversed half load (little-endian half).
• sth, sthu, sthx, sthux — corresponding stores.

IBM Reference

• AIX 7.3 — lhz (Load Half and Zero)
• AIX 7.3 — lhzu / lhzx / lhzux