Sylpheed/tools/ppc-manual/memory/lswi.md

lswi — Load String Word Immediate

Category: Memory · Form: X · Opcode: 0x7c0004aa

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
lswi	lswi	—	Load String Word Immediate

Syntax

(no disassembly template)

Encoding

lswi — form X

• Opcode word: 0x7c0004aa
• Primary opcode (bits 0–5): 31
• Extended opcode: 597
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description

Register Effects

lswi

• Reads (always): none
• Reads (conditional): none
• Writes (always): none
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

lswi

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="lswi"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_memory.cc:727
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:42
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:824
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:1521-1539

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::lswi => {
            let mut ea = if instr.ra() == 0 { 0u32 } else { ctx.gpr[instr.ra()] as u32 };
            let nb = if instr.nb() == 0 { 32 } else { instr.nb() };
            let mut rd = instr.rd();
            let mut bytes_left = nb;
            while bytes_left > 0 {
                let mut val = 0u32;
                for byte_idx in 0..4 {
                    if bytes_left == 0 { break; }
                    let b = mem.read_u8(ea) as u32;
                    val |= b << (24 - byte_idx * 8);
                    ea = ea.wrapping_add(1);
                    bytes_left -= 1;
                }
                ctx.gpr[rd] = val as u64;
                rd = (rd + 1) % 32;
            }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Byte-granular bulk load. Reads NB bytes starting at EA and packs them, big-endian, into successive GPRs starting at RT. Each filled GPR holds 4 bytes in its low word; partial last words are left- (most-significant-byte-) aligned with trailing zero bytes. The byte count NB is held in the RB field of the instruction encoding (1..31), with the special case NB = 0 meaning "32 bytes".
• Register wraparound at r31 → r0. The snapshot uses rd = (rd + 1) % 32. If the byte count is large enough to spill past r31, the next register is r0, then r1, etc. AIX docs flag the "RA in destination range" and "RB in destination range" cases as invalid; xenia does not check.
• RA0 semantics. RA = 0 selects literal zero. There is no RA post-write — lswi is not an update form.
• Big-endian byte ordering inside each word. First byte read goes into bits 0–7 of the destination GPR (most-significant byte). Xenia's loop builds val |= b << (24 - byte_idx * 8), matching that bit position.
• Last partial word. When NB is not a multiple of 4, the final GPR's unused low bytes are zero. The high bits remain whatever the load placed there.
• Alignment. The architecture allows arbitrary alignment, but real implementations may take alignment exceptions on cache-inhibited storage; xenia tolerates any address.
• Vanishingly rare in compiled code. Compilers don't emit lswi. Hand-written memcpy cores from the PowerPC SDK era used it for short copies; otherwise it appears mostly in byte-string init helpers.

Related Instructions

• lswx — register-supplied byte-count variant.
• stswi, stswx — symmetric stores.
• lmw — word-granular bulk load (multiple of 4 bytes only, no register wrap).
• lwz, lbz — scalar loads that compilers emit instead.

IBM Reference

• AIX 7.3 — lswi (Load String Word Immediate)
• PowerISA v2.07B Book II § "Load and Store String" for the invalid-form checks.