10dc260f0c
CONSOLIDATION.md Phase 6. Both lived untracked in the project root -- on one
disk, backed up by nothing.
tools/ppc-manual/ 393 files, 3.7 MB. 455 instructions, 350 family pages,
598 mnemonics resolvable through index.json, plus the
generator that produced them.
tools/run-canary.sh the oracle launcher.
🔴 THE LAUNCHER WAS BROKEN IN TWO WAYS AND IS REWRITTEN, not copied:
* it pointed at `xenia-rs/sylpheed.iso`, a SYMLINK. Wine cannot resolve one
and says "path invalid", which reads as a corrupt image rather than a path
problem -- it has cost a session before. It now points at the real file and
warns if handed a symlink.
* it hardcoded one machine's absolute paths, and named `xenia-rs`, which this
consolidation retires. Now derived from the script's own location, with
SYLPH_CANARY_BIN / SYLPH_ISO overrides and a check that each exists.
The standing constraints are in its header where someone will read them: one
emulator at a time, Canary runs MUTED, and never judge a crash or a hang from
a Bash-launched run -- a SIGKILL that looked like the binary was the editor's
process supervisor.
⚠️ The manual's GENERATOR reads the xenia-rs source tree, which is going away.
Its decoder now lives here as crates/sylpheed-ppc, so the generator must be
repointed before it is run again. Recorded in the README rather than left for
someone to discover; the manual's content is checked in and regenerates from
nothing implicitly.
Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
178 lines
7.6 KiB
Markdown
178 lines
7.6 KiB
Markdown
# `stvx` — Store Vector Indexed
|
||
|
||
> **Category:** [Memory](../categories/memory.md) · **Form:** [X](../forms/X.md) · **Opcode:** `0x7c0001ce`
|
||
|
||
<!-- GENERATED: BEGIN -->
|
||
|
||
## Assembler Mnemonics
|
||
|
||
| Mnemonic | XML entry | Flags | Description |
|
||
| --- | --- | --- | --- |
|
||
| `stvx` | `stvx` | — | Store Vector Indexed |
|
||
| `stvx128` | `stvx128` | — | Store Vector Indexed 128 |
|
||
|
||
## Syntax
|
||
|
||
```asm
|
||
stvx [VS], [RA0], [RB]
|
||
stvx128 [VS], [RA0], [RB]
|
||
```
|
||
|
||
## Encoding
|
||
|
||
### `stvx` — form `X`
|
||
|
||
- **Opcode word:** `0x7c0001ce`
|
||
- **Primary opcode (bits 0–5):** `31`
|
||
- **Extended opcode:** `231`
|
||
- **Synchronising:** no
|
||
|
||
| Bits | Field | Meaning |
|
||
| --- | --- | --- |
|
||
| 0–5 | `OPCD` | primary opcode |
|
||
| 6–10 | `RT/FRT/VRT` | destination |
|
||
| 11–15 | `RA/FRA/VRA` | source A |
|
||
| 16–20 | `RB/FRB/VRB` | source B |
|
||
| 21–30 | `XO` | extended opcode (10 bits) |
|
||
| 31 | `Rc` | record-form flag |
|
||
|
||
### `stvx128` — form `VX128_1`
|
||
|
||
- **Opcode word:** `0x100001c3`
|
||
- **Primary opcode (bits 0–5):** `4`
|
||
- **Extended opcode:** `451`
|
||
- **Synchronising:** no
|
||
|
||
| Bits | Field | Meaning |
|
||
| --- | --- | --- |
|
||
| 0–5 | `OPCD` | primary opcode (4) |
|
||
| 6–10 | `VD128l` | destination low 5 bits |
|
||
| 11–15 | `RA` | address register |
|
||
| 16–20 | `RB` | offset register |
|
||
| 21–27 | `XO` | extended opcode |
|
||
| 28–29 | `VD128h` | destination high 2 bits |
|
||
| 30–31 | `—` | reserved |
|
||
|
||
## Operands
|
||
|
||
| Field | Role | Description |
|
||
| --- | --- | --- |
|
||
| `VS` | stvx: read; stvx128: read | Source vector register (alias for VD on stores). |
|
||
| `RA0` | stvx: read; stvx128: read | Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, **not** `r0`. |
|
||
| `RB` | stvx: read; stvx128: read | Source GPR. |
|
||
|
||
## Register Effects
|
||
|
||
### `stvx`
|
||
|
||
- **Reads (always):** `VS`, `RA0`, `RB`
|
||
- **Reads (conditional):** _none_
|
||
- **Writes (always):** _none_
|
||
- **Writes (conditional):** _none_
|
||
|
||
### `stvx128`
|
||
|
||
- **Reads (always):** `VS`, `RA0`, `RB`
|
||
- **Reads (conditional):** _none_
|
||
- **Writes (always):** _none_
|
||
- **Writes (conditional):** _none_
|
||
|
||
## Status-Register Effects
|
||
|
||
_No condition-register or status-register effects._
|
||
|
||
## Operation (pseudocode)
|
||
|
||
```
|
||
EA <- ((RA|0) + (RB)) & ~0xF ; align to 16
|
||
MEM(EA, 16) <- byteswap(VS)
|
||
```
|
||
|
||
## C Translation Example
|
||
|
||
```c
|
||
/* stvx VS, RA, RB — 16-byte aligned store of a vector register */
|
||
uint64_t base = (insn.RA == 0) ? 0 : r[insn.RA];
|
||
uint32_t ea = (uint32_t)((base + r[insn.RB]) & ~(uint64_t)0xF);
|
||
mem_write_vec128_be(ea, v[insn.VS]);
|
||
```
|
||
|
||
## Implementation References
|
||
|
||
**`stvx`**
|
||
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="stvx"`](../../xenia-canary/tools/ppc-instructions.xml)
|
||
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:193`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L193)
|
||
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:79`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L79)
|
||
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:791`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L791)
|
||
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:1849-1859`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L1849-L1859)
|
||
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
|
||
|
||
```rust
|
||
PpcOpcode::stvx => {
|
||
let ea = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
|
||
let ea = (ea.wrapping_add(ctx.gpr[instr.rb()]) & !0xF) as u32;
|
||
// PPCBUG-511: stvx was missing invalidate_for_write.
|
||
if let Some(t) = ctx.reservation_table.as_ref().filter(|t| t.is_enabled()) {
|
||
if t.has_active_reservers() { t.invalidate_for_write(ea); }
|
||
}
|
||
let bytes = ctx.vr[instr.rs()].as_bytes();
|
||
for i in 0..16 { mem.write_u8(ea + i as u32, bytes[i]); }
|
||
ctx.pc += 4;
|
||
}
|
||
```
|
||
</details>
|
||
|
||
**`stvx128`**
|
||
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="stvx128"`](../../xenia-canary/tools/ppc-instructions.xml)
|
||
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:196`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L196)
|
||
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:79`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L79)
|
||
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:417`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L417)
|
||
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:1860-1870`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L1860-L1870)
|
||
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
|
||
|
||
```rust
|
||
PpcOpcode::stvx128 => {
|
||
let ea = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
|
||
let ea = (ea.wrapping_add(ctx.gpr[instr.rb()]) & !0xF) as u32;
|
||
// PPCBUG-511: stvx128 was missing invalidate_for_write.
|
||
if let Some(t) = ctx.reservation_table.as_ref().filter(|t| t.is_enabled()) {
|
||
if t.has_active_reservers() { t.invalidate_for_write(ea); }
|
||
}
|
||
let bytes = ctx.vr[instr.vs128()].as_bytes();
|
||
for i in 0..16 { mem.write_u8(ea + i as u32, bytes[i]); }
|
||
ctx.pc += 4;
|
||
}
|
||
```
|
||
</details>
|
||
|
||
<!-- GENERATED: END -->
|
||
|
||
## Extended Pseudocode
|
||
|
||
```
|
||
EA <- ((RA|0) + (RB)) & ~0xF ; force 16-byte alignment
|
||
MEM(EA, 16) <- byte_order_adjusted(VS) ; lane 0 at EA, lane 15 at EA+15
|
||
```
|
||
|
||
## Special Cases & Edge Conditions
|
||
|
||
- **Alignment is forced, not checked.** The low four bits of the effective address are **cleared** before the store — alignment violations silently corrupt adjacent data rather than trap. This differs from scalar `stw` (no alignment enforcement) and from `stvewx` (which stores only one element and keeps the exact EA).
|
||
- **Big-endian lane layout.** Vector lane 0 (the most-significant bytes of the 128-bit register) lives at the lowest address; lane 15 at `EA + 15`. On little-endian hosts the whole 16-byte block is byte-swapped at the memory boundary so the PowerPC-visible layout is preserved. Xenia's helper `mem_write_vec128_be` handles this.
|
||
- **`RA0` semantics.** When `RA = 0` the base is the literal zero — just like scalar loads/stores. Combined with the alignment mask this lets `stvx VS, 0, RB` store to address `RB & ~0xF`.
|
||
- **No update form.** Unlike scalar stores, VMX stores have no `u` variant that post-writes the base. Use [`stvxl`](stvxl.md) for the cache-hint variant (suggests "last" — the line is not expected to be reused soon).
|
||
- **VMX128 sibling (`stvx128`).** Identical semantics; the only difference is the operand encoding. VMX128 uses a 7-bit register index split across three non-contiguous bit fields (`VS128l ‖ VS128h`) so it can address `v0..v127` instead of the 32-register Altivec space. All alignment, byte-order and `RA0` rules are the same.
|
||
- **Read-before-write.** The 16-byte write occurs as one conceptual store; subsequent loads from the same address observe the complete new value. There's no split-transaction window visible to software.
|
||
|
||
## Related Instructions
|
||
|
||
- [`lvx`](lvx.md), [`lvx128`](lvx.md) — the load counterparts.
|
||
- [`stvxl`](stvxl.md), [`stvxl128`](stvxl.md) — cache-hint "last-use" variants.
|
||
- [`stvebx`](stvebx.md) / [`stvehx`](stvehx.md) / [`stvewx`](stvewx.md) — store single element (byte / half / word) at the exact (unaligned) address.
|
||
- [`stvlx`](stvlx.md) / [`stvrx`](stvrx.md) — store-left / store-right for unaligned vector I/O.
|
||
- [`dcbz`](dcbz.md) — zero a cache line; often paired with `stvx` in block-fill idioms.
|
||
|
||
## IBM Reference
|
||
|
||
- [AIX 7.3 — `stvx` (Store Vector Indexed)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-stvx-store-vector-indexed-instruction)
|
||
- PowerISA Book II (Altivec / VMX). Xbox 360 VMX128 is Microsoft-documented in the XDK; xenia's `ppc-instructions.xml` captures the deltas.
|