10dc260f0c
CONSOLIDATION.md Phase 6. Both lived untracked in the project root -- on one
disk, backed up by nothing.
tools/ppc-manual/ 393 files, 3.7 MB. 455 instructions, 350 family pages,
598 mnemonics resolvable through index.json, plus the
generator that produced them.
tools/run-canary.sh the oracle launcher.
🔴 THE LAUNCHER WAS BROKEN IN TWO WAYS AND IS REWRITTEN, not copied:
* it pointed at `xenia-rs/sylpheed.iso`, a SYMLINK. Wine cannot resolve one
and says "path invalid", which reads as a corrupt image rather than a path
problem -- it has cost a session before. It now points at the real file and
warns if handed a symlink.
* it hardcoded one machine's absolute paths, and named `xenia-rs`, which this
consolidation retires. Now derived from the script's own location, with
SYLPH_CANARY_BIN / SYLPH_ISO overrides and a check that each exists.
The standing constraints are in its header where someone will read them: one
emulator at a time, Canary runs MUTED, and never judge a crash or a hang from
a Bash-launched run -- a SIGKILL that looked like the binary was the editor's
process supervisor.
⚠️ The manual's GENERATOR reads the xenia-rs source tree, which is going away.
Its decoder now lives here as crates/sylpheed-ppc, so the generator must be
repointed before it is run again. Recorded in the README rather than left for
someone to discover; the manual's content is checked in and regenerates from
nothing implicitly.
Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
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vsl — Vector Shift Left
Category: VMX (Altivec) · Form: VX · Opcode:
0x100001c4
Assembler Mnemonics
| Mnemonic | XML entry | Flags | Description |
|---|---|---|---|
vsl |
vsl |
— | Vector Shift Left |
Syntax
vsl [VD], [VA], [VB]
Encoding
vsl — form VX
- Opcode word:
0x100001c4 - Primary opcode (bits 0–5):
4 - Extended opcode:
452 - Synchronising: no
| Bits | Field | Meaning |
|---|---|---|
| 0–5 | OPCD |
primary opcode (4) |
| 6–10 | VRT/VD |
destination vector register |
| 11–15 | VRA/VA |
source A vector register |
| 16–20 | VRB/VB |
source B vector register |
| 21–31 | XO |
extended opcode (11 bits) |
Operands
| Field | Role | Description |
|---|---|---|
VA |
vsl: read | Source A vector register. |
VB |
vsl: read | Source B vector register. |
VD |
vsl: write | Destination vector register. |
Register Effects
vsl
- Reads (always):
VA,VB - Reads (conditional): none
- Writes (always):
VD - Writes (conditional): none
Status-Register Effects
No condition-register or status-register effects.
Operation (pseudocode)
; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
; - Read source operands from the fields listed under Operands.
; - Apply the arithmetic / logical / memory action described
; in the Description field above.
; - Write results to the destination register(s); update any
; status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.
C Translation Example
/* C translation: the xenia-rs interpreter arm below in */
/* Implementation References is the authoritative semantic */
/* snapshot. Translate it line-by-line: */
/* - ctx.gpr[N] -> r[N] (or f[]/v[] for FPRs/VRs) */
/* - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be */
/* - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v) */
/* - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO */
/* The Register Effects and Status-Register Effects tables above */
/* enumerate every side effect a faithful translation must emit. */
Implementation References
vsl
- xenia-canary XML:
tools/ppc-instructions.xml— search formnem="vsl" - xenia-canary emit:
src/xenia/cpu/ppc/ppc_emit_altivec.cc:1402 - xenia-rs opcode:
crates/xenia-cpu/src/opcode.rs:122 - xenia-rs decoder:
crates/xenia-cpu/src/decoder.rs:472 - xenia-rs interpreter:
crates/xenia-cpu/src/interpreter.rs:3920-3926
xenia-rs interpreter body (frozen snapshot)
PpcOpcode::vsl => {
let a = u128::from_be_bytes(ctx.vr[instr.ra()].as_bytes());
let shift = (ctx.vr[instr.rb()].as_bytes()[15] & 7) as u32;
let r = if shift == 0 { a } else { a << shift };
ctx.vr[instr.rd()] = xenia_types::Vec128::from_bytes(r.to_be_bytes());
ctx.pc += 4;
}
Special Cases & Edge Conditions
- Whole-register bit shift-left. The 128-bit value
VAis shifted left byNbits, whereN = VB.b[15] & 7— i.e. the low 3 bits of the last (least-significant) byte ofVB. Bits shifted out the top are discarded; zero-fill on the right. - Shift count constraint. The ISA requires the same 3-bit shift count in all 16 bytes of
VB; behaviour is undefined otherwise (xenia-rs reads only byte 15 as above). Compilers guarantee this by splatting the shift count first. - Combine with
vslofor up to 127-bit shifts.vslohandles the byte-granular component;vslpicks up the remaining 0..7 bits. The canonical 128-bit shift-left isvslofollowed byvsl. - Big-endian. "Left" means toward the MSB end of the register.
- No flags, no VSCR.
- No VMX128 sibling.
Related Instructions
vslo— whole-register shift-left by octets (bytes).vsr,vsro— the right-shift counterparts.vsldoi— static-immediate byte shift ofVA ‖ VB.vslb,vslh,vslw— per-lane logical shifts.