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Sylpheed/tools/ppc-manual/forms/VX.md
MechaCat02 10dc260f0c chore(tools): adopt the PPC manual and a canary launcher that works anywhere 
CONSOLIDATION.md Phase 6. Both lived untracked in the project root -- on one
disk, backed up by nothing.

  tools/ppc-manual/   393 files, 3.7 MB. 455 instructions, 350 family pages,
                      598 mnemonics resolvable through index.json, plus the
                      generator that produced them.
  tools/run-canary.sh the oracle launcher.

🔴 THE LAUNCHER WAS BROKEN IN TWO WAYS AND IS REWRITTEN, not copied:

  * it pointed at `xenia-rs/sylpheed.iso`, a SYMLINK. Wine cannot resolve one
    and says "path invalid", which reads as a corrupt image rather than a path
    problem -- it has cost a session before. It now points at the real file and
    warns if handed a symlink.
  * it hardcoded one machine's absolute paths, and named `xenia-rs`, which this
    consolidation retires. Now derived from the script's own location, with
    SYLPH_CANARY_BIN / SYLPH_ISO overrides and a check that each exists.

The standing constraints are in its header where someone will read them: one
emulator at a time, Canary runs MUTED, and never judge a crash or a hang from
a Bash-launched run -- a SIGKILL that looked like the binary was the editor's
process supervisor.

⚠️ The manual's GENERATOR reads the xenia-rs source tree, which is going away.
Its decoder now lives here as crates/sylpheed-ppc, so the generator must be
repointed before it is run again. Recorded in the README rather than left for
someone to discover; the manual's content is checked in and regenerates from
nothing implicitly.

Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
2026-09-13 21:18:00 +02:00

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This file contains ambiguous Unicode characters
This file contains Unicode characters that might be confused with other characters. If you think that this is intentional, you can safely ignore this warning. Use the Escape button to reveal them.
# Form `VX` — VX — Vector (3-operand Altivec)
## Bit Layout
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VRT/VD` | destination vector register |
| 11–15 | `VRA/VA` | source A vector register |
| 16–20 | `VRB/VB` | source B vector register |
| 21–31 | `XO` | extended opcode (11 bits) |
## Instructions Using This Form
<!-- GENERATED: BEGIN -->
| Mnemonic | Opcode | Group | Description |
| --- | --- | --- | --- |
| [`vaddubm`](../vmx/vaddubm.md) | `0x10000000` | vmx | Vector Add Unsigned Byte Modulo |
| [`vmaxub`](../vmx/vmaxub.md) | `0x10000002` | vmx | Vector Maximum Unsigned Byte |
| [`vrlb`](../vmx/vrlb.md) | `0x10000004` | vmx | Vector Rotate Left Integer Byte |
| [`vmuloub`](../vmx/vmuloub.md) | `0x10000008` | vmx | Vector Multiply Odd Unsigned Byte |
| [`vaddfp`](../vmx/vaddfp.md) | `0x1000000a` | vmx | Vector Add Floating Point |
| [`vmrghb`](../vmx/vmrghb.md) | `0x1000000c` | vmx | Vector Merge High Byte |
| [`vpkuhum`](../vmx/vpkuhum.md) | `0x1000000e` | vmx | Vector Pack Unsigned Half Word Unsigned Modulo |
| [`vadduhm`](../vmx/vadduhm.md) | `0x10000040` | vmx | Vector Add Unsigned Half Word Modulo |
| [`vmaxuh`](../vmx/vmaxuh.md) | `0x10000042` | vmx | Vector Maximum Unsigned Half Word |
| [`vrlh`](../vmx/vrlh.md) | `0x10000044` | vmx | Vector Rotate Left Integer Half Word |
| [`vmulouh`](../vmx/vmulouh.md) | `0x10000048` | vmx | Vector Multiply Odd Unsigned Half Word |
| [`vsubfp`](../vmx/vsubfp.md) | `0x1000004a` | vmx | Vector Subtract Floating Point |
| [`vmrghh`](../vmx/vmrghh.md) | `0x1000004c` | vmx | Vector Merge High Half Word |
| [`vpkuwum`](../vmx/vpkuwum.md) | `0x1000004e` | vmx | Vector Pack Unsigned Word Unsigned Modulo |
| [`vadduwm`](../vmx/vadduwm.md) | `0x10000080` | vmx | Vector Add Unsigned Word Modulo |
| [`vmaxuw`](../vmx/vmaxuw.md) | `0x10000082` | vmx | Vector Maximum Unsigned Word |
| [`vrlw`](../vmx/vrlw.md) | `0x10000084` | vmx | Vector Rotate Left Integer Word |
| [`vmrghw`](../vmx/vmrghw.md) | `0x1000008c` | vmx | Vector Merge High Word |
| [`vpkuhus`](../vmx/vpkuhus.md) | `0x1000008e` | vmx | Vector Pack Unsigned Half Word Unsigned Saturate |
| [`vpkuwus`](../vmx/vpkuwus.md) | `0x100000ce` | vmx | Vector Pack Unsigned Word Unsigned Saturate |
| [`vmaxsb`](../vmx/vmaxsb.md) | `0x10000102` | vmx | Vector Maximum Signed Byte |
| [`vslb`](../vmx/vslb.md) | `0x10000104` | vmx | Vector Shift Left Integer Byte |
| [`vmulosb`](../vmx/vmulosb.md) | `0x10000108` | vmx | Vector Multiply Odd Signed Byte |
| [`vrefp`](../vmx/vrefp.md) | `0x1000010a` | vmx | Vector Reciprocal Estimate Floating Point |
| [`vmrglb`](../vmx/vmrglb.md) | `0x1000010c` | vmx | Vector Merge Low Byte |
| [`vpkshus`](../vmx/vpkshus.md) | `0x1000010e` | vmx | Vector Pack Signed Half Word Unsigned Saturate |
| [`vmaxsh`](../vmx/vmaxsh.md) | `0x10000142` | vmx | Vector Maximum Signed Half Word |
| [`vslh`](../vmx/vslh.md) | `0x10000144` | vmx | Vector Shift Left Integer Half Word |
| [`vmulosh`](../vmx/vmulosh.md) | `0x10000148` | vmx | Vector Multiply Odd Signed Half Word |
| [`vrsqrtefp`](../vmx/vrsqrtefp.md) | `0x1000014a` | vmx | Vector Reciprocal Square Root Estimate Floating Point |
| [`vmrglh`](../vmx/vmrglh.md) | `0x1000014c` | vmx | Vector Merge Low Half Word |
| [`vpkswus`](../vmx/vpkswus.md) | `0x1000014e` | vmx | Vector Pack Signed Word Unsigned Saturate |
| [`vaddcuw`](../vmx/vaddcuw.md) | `0x10000180` | vmx | Vector Add Carryout Unsigned Word |
| [`vmaxsw`](../vmx/vmaxsw.md) | `0x10000182` | vmx | Vector Maximum Signed Word |
| [`vslw`](../vmx/vslw.md) | `0x10000184` | vmx | Vector Shift Left Integer Word |
| [`vexptefp`](../vmx/vexptefp.md) | `0x1000018a` | vmx | Vector 2 Raised to the Exponent Estimate Floating Point |
| [`vmrglw`](../vmx/vmrglw.md) | `0x1000018c` | vmx | Vector Merge Low Word |
| [`vpkshss`](../vmx/vpkshss.md) | `0x1000018e` | vmx | Vector Pack Signed Half Word Signed Saturate |
| [`vsl`](../vmx/vsl.md) | `0x100001c4` | vmx | Vector Shift Left |
| [`vlogefp`](../vmx/vlogefp.md) | `0x100001ca` | vmx | Vector Log2 Estimate Floating Point |
| [`vpkswss`](../vmx/vpkswss.md) | `0x100001ce` | vmx | Vector Pack Signed Word Signed Saturate |
| [`vaddubs`](../vmx/vaddubs.md) | `0x10000200` | vmx | Vector Add Unsigned Byte Saturate |
| [`vminub`](../vmx/vminub.md) | `0x10000202` | vmx | Vector Minimum Unsigned Byte |
| [`vsrb`](../vmx/vsrb.md) | `0x10000204` | vmx | Vector Shift Right Byte |
| [`vmuleub`](../vmx/vmuleub.md) | `0x10000208` | vmx | Vector Multiply Even Unsigned Byte |
| [`vrfin`](../vmx/vrfin.md) | `0x1000020a` | vmx | Vector Round to Floating-Point Integer Nearest |
| [`vspltb`](../vmx/vspltb.md) | `0x1000020c` | vmx | Vector Splat Byte |
| [`vupkhsb`](../vmx/vupkhsb.md) | `0x1000020e` | vmx | Vector Unpack High Signed Byte |
| [`vadduhs`](../vmx/vadduhs.md) | `0x10000240` | vmx | Vector Add Unsigned Half Word Saturate |
| [`vminuh`](../vmx/vminuh.md) | `0x10000242` | vmx | Vector Minimum Unsigned Half Word |
| [`vsrh`](../vmx/vsrh.md) | `0x10000244` | vmx | Vector Shift Right Half Word |
| [`vmuleuh`](../vmx/vmuleuh.md) | `0x10000248` | vmx | Vector Multiply Even Unsigned Half Word |
| [`vrfiz`](../vmx/vrfiz.md) | `0x1000024a` | vmx | Vector Round to Floating-Point Integer toward Zero |
| [`vsplth`](../vmx/vsplth.md) | `0x1000024c` | vmx | Vector Splat Half Word |
| [`vupkhsh`](../vmx/vupkhsh.md) | `0x1000024e` | vmx | Vector Unpack High Signed Half Word |
| [`vadduws`](../vmx/vadduws.md) | `0x10000280` | vmx | Vector Add Unsigned Word Saturate |
| [`vminuw`](../vmx/vminuw.md) | `0x10000282` | vmx | Vector Minimum Unsigned Word |
| [`vsrw`](../vmx/vsrw.md) | `0x10000284` | vmx | Vector Shift Right Word |
| [`vrfip`](../vmx/vrfip.md) | `0x1000028a` | vmx | Vector Round to Floating-Point Integer toward +Infinity |
| [`vspltw`](../vmx/vspltw.md) | `0x1000028c` | vmx | Vector Splat Word |
| [`vupklsb`](../vmx/vupklsb.md) | `0x1000028e` | vmx | Vector Unpack Low Signed Byte |
| [`vsr`](../vmx/vsr.md) | `0x100002c4` | vmx | Vector Shift Right |
| [`vrfim`](../vmx/vrfim.md) | `0x100002ca` | vmx | Vector Round to Floating-Point Integer toward -Infinity |
| [`vupklsh`](../vmx/vupklsh.md) | `0x100002ce` | vmx | Vector Unpack Low Signed Half Word |
| [`vaddsbs`](../vmx/vaddsbs.md) | `0x10000300` | vmx | Vector Add Signed Byte Saturate |
| [`vminsb`](../vmx/vminsb.md) | `0x10000302` | vmx | Vector Minimum Signed Byte |
| [`vsrab`](../vmx/vsrab.md) | `0x10000304` | vmx | Vector Shift Right Algebraic Byte |
| [`vmulesb`](../vmx/vmulesb.md) | `0x10000308` | vmx | Vector Multiply Even Signed Byte |
| [`vcfux`](../vmx/vcfux.md) | `0x1000030a` | vmx | Vector Convert from Unsigned Fixed-Point Word |
| [`vspltisb`](../vmx/vspltisb.md) | `0x1000030c` | vmx | Vector Splat Immediate Signed Byte |
| [`vpkpx`](../vmx/vpkpx.md) | `0x1000030e` | vmx | Vector Pack Pixel |
| [`vaddshs`](../vmx/vaddshs.md) | `0x10000340` | vmx | Vector Add Signed Half Word Saturate |
| [`vminsh`](../vmx/vminsh.md) | `0x10000342` | vmx | Vector Minimum Signed Half Word |
| [`vsrah`](../vmx/vsrah.md) | `0x10000344` | vmx | Vector Shift Right Algebraic Half Word |
| [`vmulesh`](../vmx/vmulesh.md) | `0x10000348` | vmx | Vector Multiply Even Signed Half Word |
| [`vcfsx`](../vmx/vcfsx.md) | `0x1000034a` | vmx | Vector Convert from Signed Fixed-Point Word |
| [`vspltish`](../vmx/vspltish.md) | `0x1000034c` | vmx | Vector Splat Immediate Signed Half Word |
| [`vupkhpx`](../vmx/vupkhpx.md) | `0x1000034e` | vmx | Vector Unpack High Pixel |
| [`vaddsws`](../vmx/vaddsws.md) | `0x10000380` | vmx | Vector Add Signed Word Saturate |
| [`vminsw`](../vmx/vminsw.md) | `0x10000382` | vmx | Vector Minimum Signed Word |
| [`vsraw`](../vmx/vsraw.md) | `0x10000384` | vmx | Vector Shift Right Algebraic Word |
| [`vctuxs`](../vmx/vctuxs.md) | `0x1000038a` | vmx | Vector Convert to Unsigned Fixed-Point Word Saturate |
| [`vspltisw`](../vmx/vspltisw.md) | `0x1000038c` | vmx | Vector Splat Immediate Signed Word |
| [`vctsxs`](../vmx/vctsxs.md) | `0x100003ca` | vmx | Vector Convert to Signed Fixed-Point Word Saturate |
| [`vupklpx`](../vmx/vupklpx.md) | `0x100003ce` | vmx | Vector Unpack Low Pixel |
| [`vsububm`](../vmx/vsububm.md) | `0x10000400` | vmx | Vector Subtract Unsigned Byte Modulo |
| [`vavgub`](../vmx/vavgub.md) | `0x10000402` | vmx | Vector Average Unsigned Byte |
| [`vand`](../vmx/vand.md) | `0x10000404` | vmx | Vector Logical AND |
| [`vmaxfp`](../vmx/vmaxfp.md) | `0x1000040a` | vmx | Vector Maximum Floating Point |
| [`vslo`](../vmx/vslo.md) | `0x1000040c` | vmx | Vector Shift Left by Octet |
| [`vsubuhm`](../vmx/vsubuhm.md) | `0x10000440` | vmx | Vector Subtract Unsigned Half Word Modulo |
| [`vavguh`](../vmx/vavguh.md) | `0x10000442` | vmx | Vector Average Unsigned Half Word |
| [`vandc`](../vmx/vandc.md) | `0x10000444` | vmx | Vector Logical AND with Complement |
| [`vminfp`](../vmx/vminfp.md) | `0x1000044a` | vmx | Vector Minimum Floating Point |
| [`vsro`](../vmx/vsro.md) | `0x1000044c` | vmx | Vector Shift Right Octet |
| [`vsubuwm`](../vmx/vsubuwm.md) | `0x10000480` | vmx | Vector Subtract Unsigned Word Modulo |
| [`vavguw`](../vmx/vavguw.md) | `0x10000482` | vmx | Vector Average Unsigned Word |
| [`vor`](../vmx/vor.md) | `0x10000484` | vmx | Vector Logical OR |
| [`vxor`](../vmx/vxor.md) | `0x100004c4` | vmx | Vector Logical XOR |
| [`vavgsb`](../vmx/vavgsb.md) | `0x10000502` | vmx | Vector Average Signed Byte |
| [`vnor`](../vmx/vnor.md) | `0x10000504` | vmx | Vector Logical NOR |
| [`vavgsh`](../vmx/vavgsh.md) | `0x10000542` | vmx | Vector Average Signed Half Word |
| [`vsubcuw`](../vmx/vsubcuw.md) | `0x10000580` | vmx | Vector Subtract Carryout Unsigned Word |
| [`vavgsw`](../vmx/vavgsw.md) | `0x10000582` | vmx | Vector Average Signed Word |
| [`vsububs`](../vmx/vsububs.md) | `0x10000600` | vmx | Vector Subtract Unsigned Byte Saturate |
| [`mfvscr`](../control/mfvscr.md) | `0x10000604` | control | Move from VSCR |
| [`vsum4ubs`](../vmx/vsum4ubs.md) | `0x10000608` | vmx | Vector Sum Across Partial (1/4) Unsigned Byte Saturate |
| [`vsubuhs`](../vmx/vsubuhs.md) | `0x10000640` | vmx | Vector Subtract Unsigned Half Word Saturate |
| [`mtvscr`](../control/mtvscr.md) | `0x10000644` | control | Move to VSCR |
| [`vsum4shs`](../vmx/vsum4shs.md) | `0x10000648` | vmx | Vector Sum Across Partial (1/4) Signed Half Word Saturate |
| [`vsubuws`](../vmx/vsubuws.md) | `0x10000680` | vmx | Vector Subtract Unsigned Word Saturate |
| [`vsum2sws`](../vmx/vsum2sws.md) | `0x10000688` | vmx | Vector Sum Across Partial (1/2) Signed Word Saturate |
| [`vsubsbs`](../vmx/vsubsbs.md) | `0x10000700` | vmx | Vector Subtract Signed Byte Saturate |
| [`vsum4sbs`](../vmx/vsum4sbs.md) | `0x10000708` | vmx | Vector Sum Across Partial (1/4) Signed Byte Saturate |
| [`vsubshs`](../vmx/vsubshs.md) | `0x10000740` | vmx | Vector Subtract Signed Half Word Saturate |
| [`vsubsws`](../vmx/vsubsws.md) | `0x10000780` | vmx | Vector Subtract Signed Word Saturate |
| [`vsumsws`](../vmx/vsumsws.md) | `0x10000788` | vmx | Vector Sum Across Signed Word Saturate |
<!-- GENERATED: END -->
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