Sylpheed/tools/ppc-manual/alu/norx.md

norx — NOR

Category: Integer ALU · Form: X · Opcode: 0x7c0000f8

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
nor	norx	—	NOR
nor.	norx	Rc=1	NOR

Syntax

nor[Rc] [RA], [RS], [RB]

Encoding

norx — form X

• Opcode word: 0x7c0000f8
• Primary opcode (bits 0–5): 31
• Extended opcode: 124
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RS	norx: read	Source GPR (alias for RD in some stores).
RB	norx: read	Source GPR.
RA	norx: write	Source GPR (r0–r31).
CR	norx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

norx

• Reads (always): RS, RB
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): CR

Status-Register Effects

• norx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

RA <- ~((RS) | (RB))

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

norx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="norx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_alu.cc:763
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:59
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:777
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:562-569

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::norx => {
            // PPCBUG-029: `not` simplified mnemonic — every `not` poisoned the GPR.
            let rs32 = ctx.gpr[instr.rs()] as u32;
            let rb32 = ctx.gpr[instr.rb()] as u32;
            ctx.gpr[instr.ra()] = (!(rs32 | rb32)) as u64;
            if instr.rc_bit() { ctx.update_cr_signed(0, ctx.gpr[instr.ra()] as u32 as i32 as i64); }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• RA ← ~(RS OR RB). Bit-wise NOR. The canonical idiom for one-instruction NOT: not RA, RS is the simplified mnemonic for nor RA, RS, RS — both source operands the same yields ~RS. Almost every disassembly contains this pattern.
• Operand convention is X-form (RA destination, RS/RB sources).
• 64-bit operation on Xenon; full 64-bit complement via ! on u64.
• No OE or XER side effects.
• Rc=1 CR0 update truncates to 32 bits in xenia-rs. interpreter.rs:372 uses as i32 as i64. Note that NOR almost always produces results with high bits set (since the OR rarely covers all 64 bits), so the truncated CR0 is usually LT (negative low half) where spec might give a different signed compare for the full 64-bit value.
• nor. after a clear-low operation is a common pattern for testing whether some high-bit mask is empty.

Related Instructions

• orx, orcx — base OR family.
• andx, andcx, nandx — AND family.
• eqvx — NXOR.
• xorx — XOR.
• not (simplified mnemonic for nor RA, RS, RS).

IBM Reference

• AIX 7.3 — nor (NOR)
• AIX 7.3 — not (simplified mnemonic)