Sylpheed/tools/ppc-manual/alu/orcx.md

orcx — OR with Complement

Category: Integer ALU · Form: X · Opcode: 0x7c000338

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
orc	orcx	—	OR with Complement
orc.	orcx	Rc=1	OR with Complement

Syntax

orc[Rc] [RA], [RS], [RB]

Encoding

orcx — form X

• Opcode word: 0x7c000338
• Primary opcode (bits 0–5): 31
• Extended opcode: 412
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RS	orcx: read	Source GPR (alias for RD in some stores).
RB	orcx: read	Source GPR.
RA	orcx: write	Source GPR (r0–r31).
CR	orcx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

orcx

• Reads (always): RS, RB
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): CR

Status-Register Effects

• orcx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

RA <- (RS) | ~(RB)

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

orcx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="orcx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_alu.cc:800
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:59
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:807
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:548-555

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::orcx => {
            // PPCBUG-028: same shape as andcx — operate in u32.
            let rs32 = ctx.gpr[instr.rs()] as u32;
            let rb32 = ctx.gpr[instr.rb()] as u32;
            ctx.gpr[instr.ra()] = (rs32 | !rb32) as u64;
            if instr.rc_bit() { ctx.update_cr_signed(0, ctx.gpr[instr.ra()] as u32 as i32 as i64); }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• RA ← RS OR (NOT RB). The complement is on RB. Useful for setting bits outside a mask — e.g. orc r3, r3, r4 sets in r3 every bit not set in r4.
• Idiom: orc RA, RS, RS = RS | ~RS = -1 (all ones). Cheaper-looking than constructing −1 via lis+ori, but the assembler usually prefers li RA, -1 or eqv RA, RS, RS.
• Operand convention is X-form (RA destination, RS/RB sources).
• 64-bit operation on Xenon; xenia uses Rust's ! on u64 for full-width complement.
• No OE or XER side effects.
• Rc=1 CR0 update truncates to 32 bits in xenia-rs. interpreter.rs:362. Because ~RB typically has high bits set, orc. results often appear LT in the truncated CR0.

Related Instructions

• orx — base OR (no complement).
• andcx — AND-with-complement; sister c form.
• norx, nandx — full-result complements.
• eqvx — ~(RS XOR RB).

IBM Reference

• AIX 7.3 — orc (OR with Complement)