6bdbf89ebc
CONSOLIDATION.md Phase 6. Both lived untracked in the project root -- on one
disk, backed up by nothing.
tools/ppc-manual/ 393 files, 3.7 MB. 455 instructions, 350 family pages,
598 mnemonics resolvable through index.json, plus the
generator that produced them.
tools/run-canary.sh the oracle launcher.
🔴 THE LAUNCHER WAS BROKEN IN TWO WAYS AND IS REWRITTEN, not copied:
* it pointed at `xenia-rs/sylpheed.iso`, a SYMLINK. Wine cannot resolve one
and says "path invalid", which reads as a corrupt image rather than a path
problem -- it has cost a session before. It now points at the real file and
warns if handed a symlink.
* it hardcoded one machine's absolute paths, and named `xenia-rs`, which this
consolidation retires. Now derived from the script's own location, with
SYLPH_CANARY_BIN / SYLPH_ISO overrides and a check that each exists.
The standing constraints are in its header where someone will read them: one
emulator at a time, Canary runs MUTED, and never judge a crash or a hang from
a Bash-launched run -- a SIGKILL that looked like the binary was the editor's
process supervisor.
⚠️ The manual's GENERATOR reads the xenia-rs source tree, which is going away.
Its decoder now lives here as crates/sylpheed-ppc, so the generator must be
repointed before it is run again. Recorded in the README rather than left for
someone to discover; the manual's content is checked in and regenerates from
nothing implicitly.
Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
4.3 KiB
4.3 KiB
ori — OR Immediate
Category: Integer ALU · Form: D · Opcode:
0x60000000
Assembler Mnemonics
| Mnemonic | XML entry | Flags | Description |
|---|---|---|---|
ori |
ori |
— | OR Immediate |
Syntax
ori [RA], [RS], [UIMM]
Encoding
ori — form D
- Opcode word:
0x60000000 - Primary opcode (bits 0–5):
24 - Extended opcode: —
- Synchronising: no
| Bits | Field | Meaning |
|---|---|---|
| 0–5 | OPCD |
primary opcode |
| 6–10 | RT |
destination GPR (or RS when storing) |
| 11–15 | RA |
source GPR (0 ⇒ literal 0 for RA0 forms) |
| 16–31 | D/SI/UI |
16-bit signed or unsigned immediate |
Operands
| Field | Role | Description |
|---|---|---|
RS |
ori: read | Source GPR (alias for RD in some stores). |
UIMM |
ori: read | 16-bit unsigned immediate. Zero-extended. |
RA |
ori: write | Source GPR (r0–r31). |
Register Effects
ori
- Reads (always):
RS,UIMM - Reads (conditional): none
- Writes (always):
RA - Writes (conditional): none
Status-Register Effects
No condition-register or status-register effects.
Operation (pseudocode)
RA <- (RS) | (0x0000 || UIMM)
C Translation Example
/* C translation: the xenia-rs interpreter arm below in */
/* Implementation References is the authoritative semantic */
/* snapshot. Translate it line-by-line: */
/* - ctx.gpr[N] -> r[N] (or f[]/v[] for FPRs/VRs) */
/* - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be */
/* - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v) */
/* - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO */
/* The Register Effects and Status-Register Effects tables above */
/* enumerate every side effect a faithful translation must emit. */
Implementation References
ori
- xenia-canary XML:
tools/ppc-instructions.xml— search formnem="ori" - xenia-canary emit:
src/xenia/cpu/ppc/ppc_emit_alu.cc:810 - xenia-rs opcode:
crates/xenia-cpu/src/opcode.rs:59 - xenia-rs decoder:
crates/xenia-cpu/src/decoder.rs:347 - xenia-rs interpreter:
crates/xenia-cpu/src/interpreter.rs:512-515
xenia-rs interpreter body (frozen snapshot)
PpcOpcode::ori => {
ctx.gpr[instr.ra()] = ctx.gpr[instr.rs()] | (instr.uimm16() as u64);
ctx.pc += 4;
}
Special Cases & Edge Conditions
- No record form. Unlike
andix,oridoes not updateCR0— there is noori.. If you need a CR update after OR-immediate, follow it withcmpwior useorxwithRc=1. - Immediate is zero-extended. Only the low 16 bits of
RAcan be affected; the high 48 bits are passed through fromRSunchanged. ori 0, 0, 0is the canonical NOP. All PowerPC NOPs assemble to this encoding (0x60000000). Disassemblers usually display this asnop.- Common idiom: build a 32-bit constant via
lis+ori.lis r3, hi16; ori r3, r3, lo16materialises any 32-bit immediate with no CR or XER disturbance. - 64-bit operation in xenia-rs.
interpreter.rs:330— fullu64OR; high bits unchanged fromRS. RA = 0readsr0(not the literal zero). Different fromaddi'sRA0semantics;oriuses the regularRAinterpretation.
Related Instructions
oris— same op with the immediate shifted left 16.orx— register-register; supportsRc=1.xori,xoris,andix,andisx— sister immediate logicals.nop(simplified) —ori 0, 0, 0.