Sylpheed/tools/ppc-manual/alu/oris.md

oris — OR Immediate Shifted

Category: Integer ALU · Form: D · Opcode: 0x64000000

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
oris	oris	—	OR Immediate Shifted

Syntax

oris [RA], [RS], [UIMM]

Encoding

oris — form D

• Opcode word: 0x64000000
• Primary opcode (bits 0–5): 25
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT	destination GPR (or RS when storing)
11–15	RA	source GPR (0 ⇒ literal 0 for RA0 forms)
16–31	D/SI/UI	16-bit signed or unsigned immediate

Operands

Field	Role	Description
RS	oris: read	Source GPR (alias for RD in some stores).
UIMM	oris: read	16-bit unsigned immediate. Zero-extended.
RA	oris: write	Source GPR (r0–r31).

Register Effects

oris

• Reads (always): RS, UIMM
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

RA <- (RS) | (UIMM || 0x0000)

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

oris

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="oris"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_alu.cc:821
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:59
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:348
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:516-519

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::oris => {
            ctx.gpr[instr.ra()] = ctx.gpr[instr.rs()] | ((instr.uimm16() as u64) << 16);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• No record form. No oris. — same as ori. For CR0 updates use orx with Rc=1.
• Immediate is zero-extended then shifted left 16. Only bits 32–47 of RA (in PowerISA bit numbering) can be affected; the high 32 bits and low 16 bits of RA come from RS unchanged.
• Common pair with lis to load a 32-bit constant: lis r3, hi16 (= addis r3, 0, hi16), then ori r3, r3, lo16. For unsigned constants whose low half has the high bit set, lis followed by ori works cleanly because ori is zero-extending; using addi instead would sign-extend lo16 and corrupt the constant.
• 64-bit operation in xenia-rs. interpreter.rs:334.
• No XER, no CR effect. Pure register OR.
• RA = 0 reads r0 (not literal zero); see ori.

Related Instructions

• ori — companion (immediate not shifted).
• addis — D-form add-immediate-shifted; pairs with ori to build constants.
• xoris, andisx — sister immediate-shifted logicals.

IBM Reference

• AIX 7.3 — oris (OR Immediate Shifted)