Sylpheed/tools/ppc-manual/alu/rlwimix.md

rlwimix — Rotate Left Word Immediate then Mask Insert

Category: Integer ALU · Form: M · Opcode: 0x50000000

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
rlwimi	rlwimix	—	Rotate Left Word Immediate then Mask Insert
rlwimi.	rlwimix	Rc=1	Rotate Left Word Immediate then Mask Insert

Syntax

rlwimi[Rc] [RA], [RS], [SH], [MB], [ME]

Encoding

rlwimix — form M

• Opcode word: 0x50000000
• Primary opcode (bits 0–5): 20
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RS	source GPR
11–15	RA	destination GPR
16–20	SH/RB	shift amount or source B
21–25	MB	mask begin
26–30	ME	mask end
31	Rc	record-form flag

Operands

Field	Role	Description
RS	rlwimix: read	Source GPR (alias for RD in some stores).
SH	rlwimix: read	Shift amount.
MB	rlwimix: read	Mask begin bit.
ME	rlwimix: read	Mask end bit.
RA	rlwimix: write	Source GPR (r0–r31).
CR	rlwimix: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

rlwimix

• Reads (always): RS, SH, MB, ME
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): CR

Status-Register Effects

• rlwimix: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

rlwimix

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="rlwimix"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_alu.cc:1010
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:61
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:344
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:737-749

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::rlwimix => {
            let rs = ctx.gpr[instr.rs()] as u32;
            let sh = instr.sh();
            let mb = instr.mb();
            let me = instr.me();
            let rotated = rs.rotate_left(sh);
            let mask = rlw_mask(mb, me);
            let ra = ctx.gpr[instr.ra()] as u32;
            ctx.gpr[instr.ra()] = ((rotated & mask) | (ra & !mask)) as u64;
            // PPCBUG-025: 32-bit ABI CR0 view.
            if instr.rc_bit() { ctx.update_cr_signed(0, ctx.gpr[instr.ra()] as u32 as i32 as i64); }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• RA ← (ROTL32(RS[32:63], SH) & MASK) | (RA[32:63] & ~MASK). Reads the low 32 bits of RS, rotates them, then inserts under the mask back into the low 32 bits of RA. The high 32 bits of RA are implementation-defined per spec; xenia-rs zeroes them (the as u32 cast at interpreter.rs:529 discards them on read, then as u64 zero-extends on write).
• Mask follows the standard MB..ME PPC convention. Both MB and ME are 5-bit fields; the mask is contiguous when MB <= ME, and wraps around (a "donut" mask: bits MB..31 and 0..ME) when MB > ME. Xenia's rlw_mask(mb, me) helper handles both cases.
• SH is 5 bits. Rotate amount is SH mod 32; values ≥ 32 are not encodable in this M-form.
• Used for bit-field insertion (insrwi RA, RS, n, b ≡ rlwimi RA, RS, 32-(b+n), b, b+n-1). Compilers emit rlwimi extensively for struct-bitfield writes.
• Rc=1 CR0 update truncates to 32 bits in xenia-rs. interpreter.rs:531. Since the high 32 bits of the result are zero, this matches spec's compare on the (defined) low half — but if a real Xenon left high bits non-zero, behaviour would diverge.
• No XER effect.

Related Instructions

• rlwinmx — same mask family but zeroes outside (no read-modify-write).
• rlwnmx — register-shift variant of rlwinm.
• rldimix — 64-bit insert cousin.
• insrwi, inslwi (simplified mnemonics for common insert patterns).

IBM Reference

• AIX 7.3 — rlwimi (Rotate Left Word Immediate then Mask Insert)