Sylpheed/tools/ppc-manual/alu/srawix.md

srawix — Shift Right Algebraic Word Immediate

Category: Integer ALU · Form: X · Opcode: 0x7c000670

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
srawi	srawix	—	Shift Right Algebraic Word Immediate
srawi.	srawix	Rc=1	Shift Right Algebraic Word Immediate

Syntax

srawi[Rc] [RA], [RS], [SH]

Encoding

srawix — form X

• Opcode word: 0x7c000670
• Primary opcode (bits 0–5): 31
• Extended opcode: 824
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RS	srawix: read	Source GPR (alias for RD in some stores).
SH	srawix: read	Shift amount.
RA	srawix: write	Source GPR (r0–r31).
CR	srawix: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.
CA	srawix: write	XER[CA] carry bit. Read by add-with-carry/subtract-with-borrow instructions, written by carrying instructions.

Register Effects

srawix

• Reads (always): RS, SH
• Reads (conditional): none
• Writes (always): RA, CA
• Writes (conditional): CR

Status-Register Effects

• srawix: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.; XER[CA] ← carry-out of the add / borrow-in of the subtract (always).

Operation (pseudocode)

RA <- ((RS)[32:63] >>a SH) sign-extended
CA <- (RS[32] signed) && any_low_bit_shifted_out

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

srawix

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="srawix"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_alu.cc:1291
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:65
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:843
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:661-675

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::srawix => {
            // PPCBUG-042+043 coupled: same shape as srawx for the sh-immediate form.
            let rs = ctx.gpr[instr.rs()] as i32;
            let sh = instr.sh();
            if sh == 0 {
                ctx.gpr[instr.ra()] = rs as u32 as u64;
                ctx.xer_ca = 0;
            } else {
                let result = rs >> sh;
                ctx.xer_ca = if rs < 0 && (rs as u32) << (32 - sh) != 0 { 1 } else { 0 };
                ctx.gpr[instr.ra()] = result as u32 as u64;
            }
            if instr.rc_bit() { ctx.update_cr_signed(0, ctx.gpr[instr.ra()] as u32 as i32 as i64); }
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• RA ← ((i32)RS >> SH) sign-extended with XER[CA] set when RS is negative AND any low bit was shifted out.
• SH is 5 bits (immediate, range 0..31). Unlike srawx, there is no saturation case because the count cannot exceed 31. Xenia reads it via instr.sh().
• SH = 0 sign-extends RS[32:63] to 64 bits and clears CA. This is not a no-op when RS's high 32 bits differ from the sign extension of bit 32.
• Common idiom: srawi rA, rS, 31 materialises the 32-bit sign of rS as 0 or −1 — the canonical "sign mask" pattern. Often used for branchless abs or conditional negation.
• Idiom: srawi rA, rS, n; addze rA, rA — divide signed by 2^n rounding toward zero.
• Rc=1 CR0 update truncates to 32 bits in xenia-rs. interpreter.rs:457 — matches spec because the sign-extended result has consistent low/high 32-bit signs.
• No OE bit.

Related Instructions

• srawx — register-shift form.
• sradix, sradx — 64-bit arithmetic right.
• addzex — divide-rounding companion.
• extswx — srawi rA, rS, 0 is functionally a sign-extend-32-to-64 plus CA = 0 clear; extsw is preferred when CA isn't wanted.

IBM Reference

• AIX 7.3 — srawi (Shift Right Algebraic Word Immediate)