6bdbf89ebc
CONSOLIDATION.md Phase 6. Both lived untracked in the project root -- on one
disk, backed up by nothing.
tools/ppc-manual/ 393 files, 3.7 MB. 455 instructions, 350 family pages,
598 mnemonics resolvable through index.json, plus the
generator that produced them.
tools/run-canary.sh the oracle launcher.
🔴 THE LAUNCHER WAS BROKEN IN TWO WAYS AND IS REWRITTEN, not copied:
* it pointed at `xenia-rs/sylpheed.iso`, a SYMLINK. Wine cannot resolve one
and says "path invalid", which reads as a corrupt image rather than a path
problem -- it has cost a session before. It now points at the real file and
warns if handed a symlink.
* it hardcoded one machine's absolute paths, and named `xenia-rs`, which this
consolidation retires. Now derived from the script's own location, with
SYLPH_CANARY_BIN / SYLPH_ISO overrides and a check that each exists.
The standing constraints are in its header where someone will read them: one
emulator at a time, Canary runs MUTED, and never judge a crash or a hang from
a Bash-launched run -- a SIGKILL that looked like the binary was the editor's
process supervisor.
⚠️ The manual's GENERATOR reads the xenia-rs source tree, which is going away.
Its decoder now lives here as crates/sylpheed-ppc, so the generator must be
repointed before it is run again. Recorded in the README rather than left for
someone to discover; the manual's content is checked in and regenerates from
nothing implicitly.
Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
4.8 KiB
4.8 KiB
crnand — Condition Register NAND
Category: Control / CR / SPR · Form: XL · Opcode:
0x4c0001c2
Assembler Mnemonics
| Mnemonic | XML entry | Flags | Description |
|---|---|---|---|
crnand |
crnand |
— | Condition Register NAND |
Syntax
crnand [CRBD], [CRBA], [CRBB]
Encoding
crnand — form XL
- Opcode word:
0x4c0001c2 - Primary opcode (bits 0–5):
19 - Extended opcode:
225 - Synchronising: no
| Bits | Field | Meaning |
|---|---|---|
| 0–5 | OPCD |
primary opcode (19) |
| 6–10 | BT/BO |
target / branch options |
| 11–15 | BA/BI |
source A / CR bit to test |
| 16–20 | BB |
source B |
| 21–30 | XO |
extended opcode (10 bits) |
| 31 | LK |
link flag |
Operands
| Field | Role | Description |
|---|---|---|
CRBA |
crnand: read | CR source bit A (0–31). |
CRBB |
crnand: read | CR source bit B (0–31). |
CRBD |
crnand: write | CR destination bit (0–31). |
Register Effects
crnand
- Reads (always):
CRBA,CRBB - Reads (conditional): none
- Writes (always):
CRBD - Writes (conditional): none
Status-Register Effects
No condition-register or status-register effects.
Operation (pseudocode)
; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
; - Read source operands from the fields listed under Operands.
; - Apply the arithmetic / logical / memory action described
; in the Description field above.
; - Write results to the destination register(s); update any
; status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.
C Translation Example
/* C translation: the xenia-rs interpreter arm below in */
/* Implementation References is the authoritative semantic */
/* snapshot. Translate it line-by-line: */
/* - ctx.gpr[N] -> r[N] (or f[]/v[] for FPRs/VRs) */
/* - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be */
/* - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v) */
/* - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO */
/* The Register Effects and Status-Register Effects tables above */
/* enumerate every side effect a faithful translation must emit. */
Implementation References
crnand
- xenia-canary XML:
tools/ppc-instructions.xml— search formnem="crnand" - xenia-canary emit:
src/xenia/cpu/ppc/ppc_emit_control.cc:379 - xenia-rs opcode:
crates/xenia-cpu/src/opcode.rs:17 - xenia-rs decoder:
crates/xenia-cpu/src/decoder.rs:716
Special Cases & Edge Conditions
- Operation.
CR[CRBD] ← ¬(CR[CRBA] AND CR[CRBB]). Result is 0 only when both source bits are 1; otherwise 1. - Bit-level operands. 5-bit absolute CR-bit indices, identical to the rest of the CR-logical family. Source and destination bits may all be in different CR fields.
- Identity case.
crnand BT, BA, BA≡¬CR[BA]— a one-instruction CR-bit invert. Less common thancrxoragainst acrset-prepared 1-bit, but legal. - Use case. Branch on "NOT (A AND B)". Less common than the De Morgan equivalent (
cror BT, ¬A, ¬B), but saves an extracrnotstep. - No
Rc/OE. No CR0 / XER side effects. - Not synchronising. Reorderable.
- xenia status. Decoded by the generic XL-form CR-logical handler; the interpreter snapshot is shared with
crand/cror/etc. xenia-canary'sInstrEmit_crnandemits a host AND followed by NOT.
Related Instructions
crand,crandc— non-negated AND siblings.crnor— negated OR (the De Morgan dual).cror,crorc— OR family.crxor,creqv— XOR / XNOR.mcrf— copy a 4-bit CR field wholesale.bcx— typical consumer.
crnand has no dedicated simplified mnemonic. Use crand + a separate complement, or use crnand BT, BA, BA to invert a single bit.