Sylpheed/tools/ppc-manual/memory/lvewx.md

lvewx — Load Vector Element Word Indexed

Category: Memory · Form: X · Opcode: 0x7c00008e

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
lvewx	lvewx	—	Load Vector Element Word Indexed
lvewx128	lvewx128	—	Load Vector Element Word Indexed 128

Syntax

lvewx [VD], [RA0], [RB]
lvewx128 [VD], [RA0], [RB]

Encoding

lvewx — form X

• Opcode word: 0x7c00008e
• Primary opcode (bits 0–5): 31
• Extended opcode: 71
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

lvewx128 — form VX128_1

• Opcode word: 0x10000083
• Primary opcode (bits 0–5): 4
• Extended opcode: 131
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VD128l	destination low 5 bits
11–15	RA	address register
16–20	RB	offset register
21–27	XO	extended opcode
28–29	VD128h	destination high 2 bits
30–31	—	reserved

Operands

Field	Role	Description
RA0	lvewx: read; lvewx128: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.
RB	lvewx: read; lvewx128: read	Source GPR.
VD	lvewx: write; lvewx128: write	Destination vector register.

Register Effects

lvewx

• Reads (always): RA0, RB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

lvewx128

• Reads (always): RA0, RB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

lvewx

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="lvewx"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:96
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:44
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:770
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:1898-1913

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::lvewx => {
            // Load a word from (EA & ~3) into vD at word slot
            // (EA & 0xF) >> 2. Other word lanes preserved (see lvebx).
            let base = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
            let ea_unaligned = base.wrapping_add(ctx.gpr[instr.rb()]) as u32;
            let ea = ea_unaligned & !0x3u32;
            let slot = ((ea_unaligned & 0xF) >> 2) as usize;
            let mut bytes = ctx.vr[instr.rd()].as_bytes();
            let w = mem.read_u32(ea);
            bytes[slot * 4]     = (w >> 24) as u8;
            bytes[slot * 4 + 1] = (w >> 16) as u8;
            bytes[slot * 4 + 2] = (w >> 8) as u8;
            bytes[slot * 4 + 3] = (w & 0xFF) as u8;
            ctx.vr[instr.rd()] = xenia_types::Vec128::from_bytes(bytes);
            ctx.pc += 4;
        }

lvewx128

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="lvewx128"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:99
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:44
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:414
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:3168-3174

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::lvewx128 => {
            let ea = ea_indexed(ctx, instr) & !0xF;
            let mut bytes = [0u8; 16];
            for i in 0..16 { bytes[i] = mem.read_u8(ea + i as u32); }
            ctx.vr[instr.vd128()] = xenia_types::Vec128::from_bytes(bytes);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Single word element load. Architecturally lvewx loads exactly four bytes from EA (which must be 4-byte aligned) and places them in the word lane (EA mod 16) >> 2 of the destination vector; the other 3 word lanes are undefined.
• EA must be word-aligned. The low two bits of EA are masked by hardware. Xenia's shared snapshot rounds further to 16-byte alignment for both lvewx and lvewx128.
• Xenia simplification — full-line read. Both lvewx and lvewx128 snapshots load the full aligned 16 bytes from ea & ~0xF into the destination vector. Architectural undefined lanes are filled deterministically.
• RA0 semantics. When RA = 0, base is literal zero.
• No update form. No lvewux exists.
• VMX128 sibling. lvewx128 shares semantics; the only difference is the operand encoding. VMX128 uses a 7-bit register index split across VD128l ‖ VD128h so it can address v0..v127 instead of the 32-register Altivec space.
• Big-endian word within the lane. The byte at the lower address is the most-significant byte of the word lane.
• Common idiom. Pair with vspltw to broadcast the loaded word to all four lanes, or with vperm to gather words from sparse memory into one vector.

Related Instructions

• lvebx, lvehx — byte and half element loads.
• lvx, lvxl — full 16-byte aligned vector loads.
• lvlx, lvrx — load-left / load-right partial-vector ops.
• stvewx — symmetric single-word store.

IBM Reference

• AIX 7.3 — lvewx (Load Vector Element Word Indexed)
• PowerISA v2.07B Book I "Vector Facility" § "Vector Load and Store" for lane-placement rules; Microsoft XDK for lvewx128.