Sylpheed/tools/ppc-manual/memory/lvrxl.md

lvrxl — Load Vector Right Indexed LRU

Category: Memory · Form: X · Opcode: 0x7c00064e

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
lvrxl	lvrxl	—	Load Vector Right Indexed LRU
lvrxl128	lvrxl128	—	Load Vector Right Indexed LRU 128

Syntax

lvrxl [VD], [RA0], [RB]
lvrxl128 [VD], [RA0], [RB]

Encoding

lvrxl — form X

• Opcode word: 0x7c00064e
• Primary opcode (bits 0–5): 31
• Extended opcode: 807
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

lvrxl128 — form VX128_1

• Opcode word: 0x10000643
• Primary opcode (bits 0–5): 4
• Extended opcode: 1603
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VD128l	destination low 5 bits
11–15	RA	address register
16–20	RB	offset register
21–27	XO	extended opcode
28–29	VD128h	destination high 2 bits
30–31	—	reserved

Operands

Field	Role	Description
RA0	lvrxl: read; lvrxl128: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.
RB	lvrxl: read; lvrxl128: read	Source GPR.
VD	lvrxl: write; lvrxl128: write	Destination vector register.

Register Effects

lvrxl

• Reads (always): RA0, RB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

lvrxl128

• Reads (always): RA0, RB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.

C Translation Example

/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

lvrxl

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="lvrxl"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:247
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:45
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:842
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:3093-3097

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::lvrx | PpcOpcode::lvrxl => {
            let ea = ea_indexed(ctx, instr);
            ctx.vr[instr.rd()] = crate::vmx::load_vector_right(mem, ea);
            ctx.pc += 4;
        }

lvrxl128

• xenia-canary XML: tools/ppc-instructions.xml — search for mnem="lvrxl128"
• xenia-canary emit: src/xenia/cpu/ppc/ppc_emit_altivec.cc:250
• xenia-rs opcode: crates/xenia-cpu/src/opcode.rs:45
• xenia-rs decoder: crates/xenia-cpu/src/decoder.rs:425
• xenia-rs interpreter: crates/xenia-cpu/src/interpreter.rs:3098-3102

xenia-rs interpreter body (frozen snapshot)

        PpcOpcode::lvrx128 | PpcOpcode::lvrxl128 => {
            let ea = ea_indexed(ctx, instr);
            ctx.vr[instr.vd128()] = crate::vmx::load_vector_right(mem, ea);
            ctx.pc += 4;
        }

Special Cases & Edge Conditions

• Same data effect as lvrx, with LRU cache hint. Reads (EA mod 16) bytes from the previous aligned line into the right half of VD; left half zero-filled. The l suffix tells the cache the line is least-recently-used.
• Hint ignored under emulation. Xenia's snapshot is shared with lvrx (PpcOpcode::lvrx | PpcOpcode::lvrxl => …).
• No alignment masking. The exact EA controls how data shifts.
• RA0 semantics. RA = 0 selects literal zero.
• Microsoft Xbox 360 specific. Part of the VMX128 / Cell BE extended set.
• Streaming-read use case. Pair with lvlxl when iterating across a buffer that will not be revisited; the LRU hint frees cache capacity for the next line.
• VMX128 sibling (lvrxl128). Identical semantics; alternative operand encoding addressing v0..v127.

Related Instructions

• lvrx, lvrx128 — non-hint variants.
• lvlxl, lvlxl128 — load-left LRU partner.
• lvxl, lvxl128 — aligned LRU vector load.
• stvrxl, stvlxl — symmetric LRU stores.

IBM Reference

• AIX 7.3 — lvrxl (Load Vector Right Indexed Last)
• PowerISA v2.07B Book I "Vector Facility"; Microsoft Xbox 360 XDK for VMX128 cache-hint behaviour.