Sylpheed/tools/ppc-manual/alu/addcx.md

addcx — Add Carrying

Category: Integer ALU · Form: XO · Opcode: 0x7c000014

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
addc	addcx	—	Add Carrying
addco	addcx	OE=1	Add Carrying
addc.	addcx	Rc=1	Add Carrying
addco.	addcx	OE=1, Rc=1	Add Carrying

Syntax

addc[OE][Rc] [RD], [RA], [RB]

Encoding

addcx — form XO

• Opcode word: 0x7c000014
• Primary opcode (bits 0–5): 31
• Extended opcode: 10
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (31)
6–10	RT	destination GPR
11–15	RA	source A
16–20	RB	source B
21	OE	overflow-enable flag
22–30	XO	extended opcode (9 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RA	addcx: read	Source GPR (r0–r31).
RB	addcx: read	Source GPR.
RD	addcx: write	Destination GPR.
CA	addcx: write	XER[CA] carry bit. Read by add-with-carry/subtract-with-borrow instructions, written by carrying instructions.
OE	addcx: write (conditional)	Overflow-enable bit. When 1, the instruction updates XER[OV] and stickies XER[SO] on signed overflow.
CR	addcx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

addcx

• Reads (always): RA, RB
• Reads (conditional): none
• Writes (always): RD, CA
• Writes (conditional): OE, CR

Status-Register Effects

• addcx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.; XER[OV] ← signed-overflow(result); XER[SO] stickies, when OE=1.; XER[CA] ← carry-out of the add / borrow-in of the subtract (always).

Operation (pseudocode)

RT <- (RA) + (RB)
CA <- carry_out_of_32_or_64_bit_add((RA), (RB))

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

addcx

• Canary XML: tools/ppc-instructions.xml — search for mnem="addcx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_alu.cc:64
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:8
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:976

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_addcx(PPCHIRBuilder& f, const InstrData& i) {
  // RD <- (RA) + (RB)
  // CA <- carry bit
  Value* ra = f.LoadGPR(i.XO.RA);
  Value* rb = f.LoadGPR(i.XO.RB);
  Value* v = f.Add(ra, rb);
  f.StoreGPR(i.XO.RT, v);
  if (i.XO.OE) {
    XEINSTRNOTIMPLEMENTED();
    // e.update_xer_with_overflow(EFLAGS OF?);
  } else {
    f.StoreCA(AddDidCarry(f, ra, rb));
  }
  if (i.XO.Rc) {
    f.UpdateCR(0, v);
  }
  return 0;
}

Special Cases & Edge Conditions

• Carry-out is mandatory. XER[CA] is updated unconditionally — addcx exists to produce the carry. It seeds a multi-word add chain that continues with addex for middle words and addzex/addmex for the final word.
• Carry detection by overflow comparison. Xenia computes CA = (result < RA) — the standard unsigned-add overflow test. Equivalent to CA = (RA + RB) >> 64 mathematically. This is correct for the 64-bit operand width that the Xenon implements; the spec also allows a 32-bit width selected by the implementation but the 970/Xenon use 64-bit add throughout.
• No trap on signed overflow. addco/addco. only set XER[OV] and sticky XER[SO]; they do not raise an exception. Xenia-rs leaves the OE branch as a // TODO (see addx for the same gap).
• 64-bit CR update on Xenon, 32-bit in xenia-rs. The Rc=1 CR0 compare reads result as i32 as i64 in interpreter.rs:97; spec demands the full 64-bit signed compare. Flag this as a xenia-rs quirk if you need bit-exact behaviour.
• XER[SO] is sticky — only mcrxr clears it. The Rc=1 form folds it into CR0[SO].
• Operand aliasing is legal, just like addx. addc r3, r3, r3 simply doubles r3 and records whether the result wrapped.

Related Instructions

• addx — same operation, but does not update XER[CA].
• addex — RA + RB + XER[CA]; chains a multi-word add after addcx.
• addmex, addzex — terminate a carry chain by adding −1 or 0 to XER[CA].
• addic, addicx — D-form immediate variants that also write XER[CA].
• subfcx — the dual: produces a borrow-out in XER[CA].

IBM Reference

• AIX 7.3 — addc (Add Carrying)
• PowerISA v2.07B, Book I, §3.3.8 — Fixed-Point Add with Carry; defines XER[CA] semantics independent of operand width.