Sylpheed/tools/ppc-manual/alu/addx.md

addx — Add

Category: Integer ALU · Form: XO · Opcode: 0x7c000214

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
add	addx	—	Add
addo	addx	OE=1	Add
add.	addx	Rc=1	Add
addo.	addx	OE=1, Rc=1	Add

Syntax

add[OE][Rc] [RD], [RA], [RB]

Encoding

addx — form XO

• Opcode word: 0x7c000214
• Primary opcode (bits 0–5): 31
• Extended opcode: 266
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (31)
6–10	RT	destination GPR
11–15	RA	source A
16–20	RB	source B
21	OE	overflow-enable flag
22–30	XO	extended opcode (9 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RA	addx: read	Source GPR (r0–r31).
RB	addx: read	Source GPR.
RD	addx: write	Destination GPR.
OE	addx: write (conditional)	Overflow-enable bit. When 1, the instruction updates XER[OV] and stickies XER[SO] on signed overflow.
CR	addx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

addx

• Reads (always): RA, RB
• Reads (conditional): none
• Writes (always): RD
• Writes (conditional): OE, CR

Status-Register Effects

• addx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.; XER[OV] ← signed-overflow(result); XER[SO] stickies, when OE=1.

Operation (pseudocode)

RT <- (RA) + (RB)

C Translation Example

/* add / add. / addo / addo.  (XO-form)                         */
uint64_t a = r[insn.RA], b = r[insn.RB];
uint64_t result = a + b;
r[insn.RT] = result;
if (insn.OE) { bool ov = (~(a ^ b) & (a ^ result)) >> 63;
               if (ov) { xer.OV = 1; xer.SO = 1; } else xer.OV = 0; }
if (insn.Rc) update_cr0_signed((int64_t)result);

Implementation References

addx

• Canary XML: tools/ppc-instructions.xml — search for mnem="addx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_alu.cc:50
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:15
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:990

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_addx(PPCHIRBuilder& f, const InstrData& i) {
  // RD <- (RA) + (RB)
  Value* v = f.Add(f.LoadGPR(i.XO.RA), f.LoadGPR(i.XO.RB));
  f.StoreGPR(i.XO.RT, v);
  if (i.XO.OE) {
    XEINSTRNOTIMPLEMENTED();
    // e.update_xer_with_overflow(EFLAGS OF?);
  }
  if (i.XO.Rc) {
    f.UpdateCR(0, v);
  }
  return 0;
}

Extended Pseudocode

RT <- (RA) + (RB)                                ; modulo 2^64, carry discarded
if OE then
    XER[OV] <- (~(RA ^ RB) & (RA ^ RT))[0]       ; signed overflow: same-sign inputs, opposite-sign result
    XER[SO] <- XER[SO] | XER[OV]
if Rc then
    CR0[LT,GT,EQ] <- signed_compare(RT, 0)        ; 64-bit comparison on the Xenon
    CR0[SO]      <- XER[SO]

Special Cases & Edge Conditions

• No trap on overflow. addo / addo. record overflow in XER[OV] and sticky-set XER[SO]. A trap can only be produced by a separate td/tw instruction examining the result.
• Signed-overflow predicate. Overflow occurs iff both addends share a sign bit and the result has the opposite sign bit: OV = ((~(a ^ b)) & (a ^ rt)) >> 63. Unsigned carry is not tracked — use addcx when you need XER[CA].
• XER[SO] is sticky. Once set, it remains set until cleared by mcrxr. The . record forms copy it into CR0[SO].
• 64-bit CR update on Xenon. The Xbox 360 Xenon CPU is 64-bit, so add. compares the full 64-bit result against zero. Xenia-rs presently truncates to 32 bits before the CR update (result as i32 as i64 in interpreter.rs:95). If your translator must match xenia bit-for-bit, emit a 32-bit compare; if it must be spec-correct, emit a 64-bit compare. Most Xbox 360 object code works either way because results that overflow 32 bits are rare outside of explicit 64-bit math.
• OE overflow detection not emulated in xenia-rs. The addo / addo. branch in interpreter.rs is a TODO stub. A faithful translator should still emit the overflow check — titles rarely observe XER[OV], but it's occasionally used by profiling / sanity-checking code paths.
• Operand aliasing. add r3, r3, r3, add r3, r3, r4, add r3, r4, r3 are all legal. The addition reads both source operands before writing RT.
• No immediate form. For RT = RA + imm use addi / addis. Those are distinct opcodes, not a flag on add.

Related Instructions

• addcx — produces the carry-out in XER[CA].
• addex — sums (RA) + (RB) + XER[CA] (carry-in chain).
• addmex, addzex — add to −1 or 0 with carry-in (used to propagate borrows across multiword subtracts).
• addi, addis — D-form immediate adds; no Rc/OE.
• addic, addicx — D-form adds that set XER[CA].
• subfx — the dual: RT ← (RB) − (RA).
• negx — two's-complement negate.

IBM Reference

• AIX 7.3 — add (Add)
• PowerISA v2.07B, Book I, §3.3.8 — Fixed-Point Arithmetic Instructions (overflow predicate, CR0 / XER[SO] semantics).