Sylpheed/tools/ppc-manual/alu/rldiclx.md

rldiclx — Rotate Left Doubleword Immediate then Clear Left

Category: Integer ALU · Form: MD · Opcode: 0x78000000

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
rldicl	rldiclx	—	Rotate Left Doubleword Immediate then Clear Left
rldicl.	rldiclx	Rc=1	Rotate Left Doubleword Immediate then Clear Left

Syntax

rldicl[Rc] [RA], [RS], [SH], [MB]

Encoding

rldiclx — form MD

• Opcode word: 0x78000000
• Primary opcode (bits 0–5): 30
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (30)
6–10	RS	source GPR
11–15	RA	destination GPR
16–20	sh	shift amount low 5 bits
21–26	mb/me	6-bit mask field (swapped halves)
27–29	XO	extended opcode
30	sh5	shift amount high bit
31	Rc	record-form flag

Operands

Field	Role	Description
RS	rldiclx: read	Source GPR (alias for RD in some stores).
SH	rldiclx: read	Shift amount.
MB	rldiclx: read	Mask begin bit.
RA	rldiclx: write	Source GPR (r0–r31).
CR	rldiclx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

rldiclx

• Reads (always): RS, SH, MB
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): CR

Status-Register Effects

• rldiclx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

rldiclx

• Canary XML: tools/ppc-instructions.xml — search for mnem="rldiclx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_alu.cc:929
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:206
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:843

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_rldiclx(PPCHIRBuilder& f, const InstrData& i) {
  // n <- sh[5] || sh[0:4]
  // r <- ROTL64((RS), n)
  // b <- mb[5] || mb[0:4]
  // m <- MASK(b, 63)
  // RA <- r & m
  uint32_t sh = (i.MD.SH5 << 5) | i.MD.SH;
  uint32_t mb = (i.MD.MB5 << 5) | i.MD.MB;
  uint64_t m = XEMASK(mb, 63);
  Value* v = f.LoadGPR(i.MD.RT);
  if (sh == 64 - mb) {
    // srdi == rldicl ra,rs,64-n,n
    v = f.Shr(v, int8_t(mb));
  } else {
    if (sh) {
      v = f.RotateLeft(v, f.LoadConstantInt8(sh));
    }
    if (m != 0xFFFFFFFFFFFFFFFF) {
      v = f.And(v, f.LoadConstantUint64(m));
    }
  }
  f.StoreGPR(i.MD.RA, v);
  if (i.MD.Rc) {
    f.UpdateCR(0, v);
  }
  return 0;
}

Special Cases & Edge Conditions

• RA ← ROTL64(RS, SH) & MASK(MB, 63). Rotate left by SH, then clear bits 0 through MB-1. The mask retains bits MB..63.
• The Swiss-army knife of bit extraction. Many assembler shorthands lower to this single instruction:
  • srdi RA, RS, n ≡ rldicl RA, RS, 64-n, n — logical right shift by n.
  • clrldi RA, RS, n ≡ rldicl RA, RS, 0, n — clear top n bits.
  • extrdi RA, RS, n, b ≡ rldicl RA, RS, b+n, 64-n — extract n bits starting at b.
• SH is 6 bits, immediate (bits 16–20 + bit 30). Xenia uses instr.sh64() to assemble them.
• MB is 6 bits, split-encoded ((instr.mb() << 1) | ((raw >> 1) & 1)).
• Rc=1 CR0 is correctly 64-bit. Uses as i64 directly (interpreter.rs:551).
• No XER effect.
• Often appears in compiled disassembly as a generic 64-bit shift. Decoding back to the simplified mnemonic above makes the intent obvious.

Related Instructions

• rldicrx — clear-right counterpart (MASK(0, ME)).
• rldicx — clear both ends.
• rldclx — register-shift version.
• rlwinmx — 32-bit cousin.
• srdi, clrldi, extrdi (simplified mnemonics).

IBM Reference

• AIX 7.3 — rldicl (Rotate Left Doubleword Immediate then Clear Left)
• AIX 7.3 — Simplified shift/extract mnemonics